1 /* 2 * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SGI_BASE_PLATFORM_DEF_H 8 #define SGI_BASE_PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/common/arm_def.h> 13 #include <plat/arm/common/arm_spm_def.h> 14 #include <plat/arm/css/common/css_def.h> 15 #include <plat/common/common_def.h> 16 17 #define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \ 18 PLAT_ARM_CLUSTER_COUNT * \ 19 CSS_SGI_MAX_CPUS_PER_CLUSTER * \ 20 CSS_SGI_MAX_PE_PER_CPU) 21 22 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 23 24 /* Remote chip address offset */ 25 #define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) \ 26 ((ULL(1) << CSS_SGI_ADDR_BITS_PER_CHIP) * (n)) 27 28 /* 29 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 30 * plat_arm_mmap array defined for each BL stage. In addition to that, on 31 * multi-chip platforms, address regions on each of the remote chips are 32 * also mapped. In BL31, for instance, three address regions on the remote 33 * chips are accessed - secure ram, css device and soc device regions. 34 */ 35 #if defined(IMAGE_BL31) 36 # if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 37 # define PLAT_ARM_MMAP_ENTRIES (10 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 38 # define MAX_XLAT_TABLES (8 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 39 # define PLAT_SP_IMAGE_MMAP_REGIONS 12 40 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 14 41 # else 42 # define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 43 # define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 44 # endif 45 #elif defined(IMAGE_BL32) 46 # define PLAT_ARM_MMAP_ENTRIES 8 47 # define MAX_XLAT_TABLES 5 48 #elif defined(IMAGE_BL2) 49 # define PLAT_ARM_MMAP_ENTRIES (11 + (CSS_SGI_CHIP_COUNT - 1)) 50 51 /* 52 * MAX_XLAT_TABLES entries need to be doubled because when the address width 53 * exceeds 40 bits an additional level of translation is required. In case of 54 * multichip platforms peripherals also fall into address space with width 55 * > 40 bits 56 * 57 */ 58 # define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 2)) 59 #elif !USE_ROMLIB 60 # define PLAT_ARM_MMAP_ENTRIES 11 61 # define MAX_XLAT_TABLES 7 62 #else 63 # define PLAT_ARM_MMAP_ENTRIES 12 64 # define MAX_XLAT_TABLES 6 65 #endif 66 67 /* 68 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 69 * plus a little space for growth. 70 */ 71 #define PLAT_ARM_MAX_BL1_RW_SIZE (64 * 1024) /* 64 KB */ 72 73 /* 74 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 75 */ 76 77 #if USE_ROMLIB 78 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 79 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 80 #else 81 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 82 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 83 #endif 84 85 /* 86 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 87 * little space for growth. Additional 8KiB space is added per chip in 88 * order to accommodate the additional level of translation required for "TZC" 89 * peripheral access which lies in >4TB address space. 90 * 91 */ 92 #if TRUSTED_BOARD_BOOT 93 # define PLAT_ARM_MAX_BL2_SIZE (0x20000 + ((CSS_SGI_CHIP_COUNT - 1) * \ 94 0x2000)) 95 #else 96 # define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((CSS_SGI_CHIP_COUNT - 1) * \ 97 0x2000)) 98 #endif 99 100 /* 101 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 102 * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2 103 * and BL1-RW. CSS_SGI_BL31_SIZE - is tuned with respect to the actual BL31 104 * PROGBITS size which is around 64-68KB at the time this change is being made. 105 * A buffer of ~35KB is added to account for future expansion of the image, 106 * making it a total of 100KB. 107 */ 108 #define CSS_SGI_BL31_SIZE (100 * 1024) /* 100 KB */ 109 #define PLAT_ARM_MAX_BL31_SIZE (CSS_SGI_BL31_SIZE + \ 110 PLAT_ARM_MAX_BL2_SIZE + \ 111 PLAT_ARM_MAX_BL1_RW_SIZE) 112 113 /* 114 * Size of cacheable stacks 115 */ 116 #if defined(IMAGE_BL1) 117 # if TRUSTED_BOARD_BOOT 118 # define PLATFORM_STACK_SIZE 0x1000 119 # else 120 # define PLATFORM_STACK_SIZE 0x440 121 # endif 122 #elif defined(IMAGE_BL2) 123 # if TRUSTED_BOARD_BOOT 124 # define PLATFORM_STACK_SIZE 0x1000 125 # else 126 # define PLATFORM_STACK_SIZE 0x400 127 # endif 128 #elif defined(IMAGE_BL2U) 129 # define PLATFORM_STACK_SIZE 0x400 130 #elif defined(IMAGE_BL31) 131 # if SPM_MM 132 # define PLATFORM_STACK_SIZE 0x500 133 # else 134 # define PLATFORM_STACK_SIZE 0x400 135 # endif 136 #elif defined(IMAGE_BL32) 137 # define PLATFORM_STACK_SIZE 0x440 138 #endif 139 140 /* PL011 UART related constants */ 141 #define SOC_CSS_SEC_UART_BASE UL(0x2A410000) 142 #define SOC_CSS_NSEC_UART_BASE UL(0x2A400000) 143 #define SOC_CSS_UART_SIZE UL(0x10000) 144 #define SOC_CSS_UART_CLK_IN_HZ UL(7372800) 145 146 /* UART related constants */ 147 #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE 148 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 149 150 #define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE 151 #define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 152 153 #define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE 154 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 155 156 #define PLAT_ARM_NSTIMER_FRAME_ID 0 157 158 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 159 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ 160 161 #define PLAT_ARM_NSRAM_BASE 0x06000000 162 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 163 164 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 165 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 166 167 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 168 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 169 170 #define CSS_SGI_DEVICE_BASE (0x20000000) 171 #define CSS_SGI_DEVICE_SIZE (0x20000000) 172 #define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ 173 CSS_SGI_DEVICE_BASE, \ 174 CSS_SGI_DEVICE_SIZE, \ 175 MT_DEVICE | MT_RW | MT_SECURE) 176 177 #define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \ 178 MAP_REGION_FLAT( \ 179 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 180 ARM_SHARED_RAM_BASE, \ 181 ARM_SHARED_RAM_SIZE, \ 182 MT_NON_CACHEABLE | MT_RW | MT_SECURE \ 183 ) 184 185 #define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \ 186 MAP_REGION_FLAT( \ 187 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 188 CSS_SGI_DEVICE_BASE, \ 189 CSS_SGI_DEVICE_SIZE, \ 190 MT_DEVICE | MT_RW | MT_SECURE \ 191 ) 192 193 #define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \ 194 MAP_REGION_FLAT( \ 195 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 196 SOC_CSS_DEVICE_BASE, \ 197 SOC_CSS_DEVICE_SIZE, \ 198 MT_DEVICE | MT_RW | MT_SECURE \ 199 ) 200 201 /* Map the secure region for access from S-EL0 */ 202 #define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ 203 SOC_CSS_DEVICE_BASE, \ 204 SOC_CSS_DEVICE_SIZE, \ 205 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 206 207 #if ENABLE_FEAT_RAS && FFH_SUPPORT 208 #define PLAT_SP_PRI PLAT_RAS_PRI 209 #else 210 #define PLAT_SP_PRI 0x10 211 #endif 212 213 #if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && ENABLE_FEAT_RAS && FFH_SUPPORT 214 /* 215 * CPER buffer memory of 128KB is reserved and it is placed adjacent to the 216 * memory shared between EL3 and S-EL0. 217 */ 218 #define CSS_SGI_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 219 PLAT_SP_IMAGE_NS_BUF_SIZE) 220 #define CSS_SGI_SP_CPER_BUF_SIZE ULL(0x20000) 221 #define CSS_SGI_SP_CPER_BUF_MMAP MAP_REGION2( \ 222 CSS_SGI_SP_CPER_BUF_BASE, \ 223 CSS_SGI_SP_CPER_BUF_BASE, \ 224 CSS_SGI_SP_CPER_BUF_SIZE, \ 225 MT_RW_DATA | MT_NS | MT_USER, \ 226 PAGE_SIZE) 227 228 /* 229 * Secure partition stack follows right after the memory space reserved for 230 * CPER buffer memory. 231 */ 232 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 233 PLAT_SP_IMAGE_NS_BUF_SIZE + \ 234 CSS_SGI_SP_CPER_BUF_SIZE) 235 #elif (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) 236 /* 237 * Secure partition stack follows right after the memory region that is shared 238 * between EL3 and S-EL0. 239 */ 240 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 241 PLAT_SP_IMAGE_NS_BUF_SIZE) 242 #endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */ 243 244 /* Platform ID address */ 245 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 246 #ifndef __ASSEMBLER__ 247 /* SSC_VERSION related accessors */ 248 /* Returns the part number of the platform */ 249 #define GET_SGI_PART_NUM \ 250 GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) 251 /* Returns the configuration number of the platform */ 252 #define GET_SGI_CONFIG_NUM \ 253 GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) 254 #endif /* __ASSEMBLER__ */ 255 256 /******************************************************************************* 257 * Memprotect definitions 258 ******************************************************************************/ 259 /* PSCI memory protect definitions: 260 * This variable is stored in a non-secure flash because some ARM reference 261 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 262 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 263 */ 264 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 265 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 266 267 /*Secure Watchdog Constants */ 268 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 269 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 270 271 /* Number of SCMI channels on the platform */ 272 #define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT 273 274 /* 275 * Mapping definition of the TrustZone Controller for ARM SGI/RD platforms 276 * where both the DRAM regions are marked for non-secure access. This applies 277 * to multi-chip platforms. 278 */ 279 #define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \ 280 {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \ 281 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \ 282 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 283 {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \ 284 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \ 285 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 286 287 #if SPM_MM 288 289 /* 290 * Stand-alone MM logs would be routed via secure UART. Define page table 291 * entry for secure UART which would be common to all platforms. 292 */ 293 #define SOC_PLATFORM_SECURE_UART MAP_REGION_FLAT( \ 294 SOC_CSS_SEC_UART_BASE, \ 295 SOC_CSS_UART_SIZE, \ 296 MT_DEVICE | MT_RW | \ 297 MT_SECURE | MT_USER) 298 299 #endif 300 301 /* SDS ID for unusable CPU MPID list structure */ 302 #define SDS_ISOLATED_CPU_LIST_ID U(128) 303 304 #endif /* SGI_BASE_PLATFORM_DEF_H */ 305
