1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) 2023, Protonic Holland - All Rights Reserved 4 * Author: David Jander <david@protonic.nl> 5 */ 6/dts-v1/; 7 8#include "stm32mp151.dtsi" 9#include "stm32mp15-pinctrl.dtsi" 10#include "stm32mp15xxad-pinctrl.dtsi" 11#include <dt-bindings/clock/stm32mp1-clksrc.h> 12#include "stm32mp15-ddr3-1x2Gb-1066-binG.dtsi" 13 14/ { 15 model = "Protonic PRTT1A"; 16 compatible = "prt,prtt1a", "st,stm32mp151"; 17 18 chosen { 19 stdout-path = "serial0:115200n8"; 20 }; 21 22 aliases { 23 mmc0 = &sdmmc1; 24 mmc1 = &sdmmc2; 25 serial0 = &uart4; 26 }; 27 28 memory@c0000000 { 29 device_type = "memory"; 30 reg = <0xC0000000 0x10000000>; 31 }; 32}; 33 34&iwdg2 { 35 timeout-sec = <32>; 36 status = "okay"; 37 secure-status = "okay"; 38}; 39 40&qspi { 41 pinctrl-names = "default", "sleep"; 42 pinctrl-0 = <&qspi_clk_pins_a 43 &qspi_bk1_pins_a 44 &qspi_cs1_pins_a>; 45 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 46 #address-cells = <1>; 47 #size-cells = <0>; 48 status = "okay"; 49 50 flash@0 { 51 compatible = "spi-nand"; 52 reg = <0>; 53 spi-rx-bus-width = <4>; 54 spi-max-frequency = <104000000>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 }; 58}; 59 60&qspi_bk1_pins_a { 61 pins { 62 bias-pull-up; 63 drive-push-pull; 64 slew-rate = <1>; 65 }; 66}; 67 68&rcc { 69 st,clksrc = < 70 CLK_MPU_PLL1P 71 CLK_AXI_PLL2P 72 CLK_MCU_PLL3P 73 CLK_PLL12_HSE 74 CLK_PLL3_HSE 75 CLK_PLL4_HSE 76 CLK_RTC_LSI 77 CLK_MCO1_DISABLED 78 CLK_MCO2_DISABLED 79 >; 80 81 st,clkdiv = < 82 1 /*MPU*/ 83 0 /*AXI*/ 84 0 /*MCU*/ 85 1 /*APB1*/ 86 1 /*APB2*/ 87 1 /*APB3*/ 88 1 /*APB4*/ 89 2 /*APB5*/ 90 23 /*RTC*/ 91 0 /*MCO1*/ 92 0 /*MCO2*/ 93 >; 94 95 st,pkcs = < 96 CLK_CKPER_HSE 97 CLK_FMC_ACLK 98 CLK_QSPI_ACLK 99 CLK_ETH_DISABLED 100 CLK_SDMMC12_PLL4P 101 CLK_DSI_DSIPLL 102 CLK_STGEN_HSE 103 CLK_USBPHY_HSE 104 CLK_SPI2S1_PLL3Q 105 CLK_SPI2S23_PLL3Q 106 CLK_SPI45_HSI 107 CLK_SPI6_HSI 108 CLK_I2C46_HSI 109 CLK_SDMMC3_PLL4P 110 CLK_USBO_USBPHY 111 CLK_ADC_CKPER 112 CLK_CEC_LSI 113 CLK_I2C12_HSI 114 CLK_I2C35_HSI 115 CLK_UART1_HSI 116 CLK_UART24_HSI 117 CLK_UART35_HSI 118 CLK_UART6_HSI 119 CLK_UART78_HSI 120 CLK_SPDIF_PLL4P 121 CLK_FDCAN_PLL4R 122 CLK_SAI1_PLL3Q 123 CLK_SAI2_PLL3Q 124 CLK_SAI3_PLL3Q 125 CLK_SAI4_PLL3Q 126 CLK_RNG1_LSI 127 CLK_RNG2_LSI 128 CLK_LPTIM1_PCLK1 129 CLK_LPTIM23_PCLK3 130 CLK_LPTIM45_LSI 131 >; 132 133 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 134 pll1: st,pll@0 { 135 compatible = "st,stm32mp1-pll"; 136 reg = <0>; 137 cfg = <2 80 0 0 0 PQR(1,0,0)>; 138 frac = <0x800>; 139 }; 140 141 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 142 pll2: st,pll@1 { 143 compatible = "st,stm32mp1-pll"; 144 reg = <1>; 145 cfg = <2 65 1 0 0 PQR(1,1,1)>; 146 frac = <0x1400>; 147 }; 148 149 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 150 pll3: st,pll@2 { 151 compatible = "st,stm32mp1-pll"; 152 reg = <2>; 153 cfg = <1 33 1 16 36 PQR(1,1,1)>; 154 frac = <0x1a04>; 155 }; 156 157 /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ 158 pll4: st,pll@3 { 159 compatible = "st,stm32mp1-pll"; 160 reg = <3>; 161 cfg = <1 39 3 11 4 PQR(1,1,1)>; 162 }; 163}; 164 165&rng1 { 166 status = "okay"; 167}; 168 169&rtc { 170 status = "okay"; 171}; 172 173&sdmmc1 { 174 pinctrl-names = "default"; 175 pinctrl-0 = <&sdmmc1_b4_pins_a>; 176 bus-width = <4>; 177 status = "okay"; 178}; 179 180&sdmmc1_b4_pins_a { 181 pins1 { 182 bias-pull-up; 183 }; 184 pins2 { 185 bias-pull-up; 186 }; 187}; 188 189/* NOTE: Although the PRTT1A does not have an eMMC, we declare it 190 * anyway, in order to be able to use the same binary for the 191 * PRTT1C also. All involved pins are N.C. on PRTT1A/S for that 192 * reason, so it should do no harm. All inputs configured with 193 * pull-ups to avoid floating inputs. */ 194&sdmmc2 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 197 bus-width = <8>; 198 status = "okay"; 199}; 200 201&sdmmc2_b4_pins_a { 202 pins1 { 203 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 204 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ 205 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 206 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 207 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 208 }; 209}; 210 211&sdmmc2_d47_pins_a { 212 pins { 213 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 214 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 215 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 216 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 217 }; 218}; 219 220&uart4 { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&uart4_pins_a>; 223 status = "okay"; 224}; 225 226&uart4_pins_a { 227 pins1 { 228 pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */ 229 bias-disable; 230 drive-push-pull; 231 slew-rate = <0>; 232 }; 233 pins2 { 234 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 235 bias-pull-up; 236 }; 237}; 238
