1 /*
2 * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/arm/css/css_scp.h>
13 #include <drivers/arm/css/scmi.h>
14 #include <lib/mmio.h>
15 #include <plat/arm/common/plat_arm.h>
16 #include <plat/arm/css/common/css_pm.h>
17 #include <plat/common/platform.h>
18 #include <platform_def.h>
19
20 /*
21 * This file implements the SCP helper functions using SCMI protocol.
22 */
23
24 /*
25 * SCMI power state parameter bit field encoding for ARM CSS platforms.
26 *
27 * 31 20 19 16 15 12 11 8 7 4 3 0
28 * +-------------------------------------------------------------+
29 * | SBZ | Max level | Level 3 | Level 2 | Level 1 | Level 0 |
30 * | | | state | state | state | state |
31 * +-------------------------------------------------------------+
32 *
33 * `Max level` encodes the highest level that has a valid power state
34 * encoded in the power state.
35 */
36 #define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 16
37 #define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4
38 #define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \
39 ((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1)
40 #define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level) \
41 (_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\
42 << SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT
43 #define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state) \
44 (((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \
45 & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)
46
47 #define SCMI_PWR_STATE_LVL_WIDTH 4
48 #define SCMI_PWR_STATE_LVL_MASK \
49 ((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1)
50 #define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state) \
51 (_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK) \
52 << (SCMI_PWR_STATE_LVL_WIDTH * (_level))
53 #define SCMI_GET_PWR_STATE_LVL(_power_state, _level) \
54 (((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) & \
55 SCMI_PWR_STATE_LVL_MASK)
56
57 /*
58 * The SCMI power state enumeration for a power domain level
59 */
60 typedef enum {
61 scmi_power_state_off = 0,
62 scmi_power_state_on = 1,
63 scmi_power_state_sleep = 2,
64 } scmi_power_state_t;
65
66 /*
67 * The global handles for invoking the SCMI driver APIs after the driver
68 * has been initialized.
69 */
70 static void *scmi_handles[PLAT_ARM_SCMI_CHANNEL_COUNT];
71
72 /* The global SCMI channels array */
73 static scmi_channel_t scmi_channels[PLAT_ARM_SCMI_CHANNEL_COUNT];
74
75 /*
76 * Channel ID for the default SCMI channel.
77 * The default channel is used to issue SYSTEM level SCMI requests and is
78 * initialized to the channel which has the boot cpu as its resource.
79 */
80 static uint32_t default_scmi_channel_id;
81
82 /*
83 * TODO: Allow use of channel specific lock instead of using a single lock for
84 * all the channels.
85 */
86 ARM_SCMI_INSTANTIATE_LOCK;
87
88 /*
89 * Function to obtain the SCMI Domain ID and SCMI Channel number from the linear
90 * core position. The SCMI Channel number is encoded in the upper 16 bits and
91 * the Domain ID is encoded in the lower 16 bits in each entry of the mapping
92 * array exported by the platform.
93 */
css_scp_core_pos_to_scmi_channel(unsigned int core_pos,unsigned int * scmi_domain_id,unsigned int * scmi_channel_id)94 static void css_scp_core_pos_to_scmi_channel(unsigned int core_pos,
95 unsigned int *scmi_domain_id, unsigned int *scmi_channel_id)
96 {
97 unsigned int composite_id;
98
99 composite_id = plat_css_core_pos_to_scmi_dmn_id_map[core_pos];
100
101 *scmi_channel_id = GET_SCMI_CHANNEL_ID(composite_id);
102 *scmi_domain_id = GET_SCMI_DOMAIN_ID(composite_id);
103 }
104
105 /*
106 * Helper function to suspend a CPU power domain and its parent power domains
107 * if applicable.
108 */
css_scp_suspend(const struct psci_power_state * target_state)109 void css_scp_suspend(const struct psci_power_state *target_state)
110 {
111 int ret;
112
113 /* At least power domain level 0 should be specified to be suspended */
114 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
115 ARM_LOCAL_STATE_OFF);
116
117 /* Check if power down at system power domain level is requested */
118 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) {
119 /* Issue SCMI command for SYSTEM_SUSPEND on all SCMI channels */
120 ret = scmi_sys_pwr_state_set(
121 scmi_handles[default_scmi_channel_id],
122 SCMI_SYS_PWR_FORCEFUL_REQ, SCMI_SYS_PWR_SUSPEND);
123 if (ret != SCMI_E_SUCCESS) {
124 ERROR("SCMI system power domain suspend return 0x%x unexpected\n",
125 ret);
126 panic();
127 }
128 return;
129 }
130 #if !HW_ASSISTED_COHERENCY
131 unsigned int lvl, channel_id, domain_id;
132 uint32_t scmi_pwr_state = 0;
133 /*
134 * If we reach here, then assert that power down at system power domain
135 * level is running.
136 */
137 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN);
138
139 /* For level 0, specify `scmi_power_state_sleep` as the power state */
140 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, ARM_PWR_LVL0,
141 scmi_power_state_sleep);
142
143 for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
144 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN)
145 break;
146
147 assert(target_state->pwr_domain_state[lvl] ==
148 ARM_LOCAL_STATE_OFF);
149 /*
150 * Specify `scmi_power_state_off` as power state for higher
151 * levels.
152 */
153 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl,
154 scmi_power_state_off);
155 }
156
157 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
158
159 css_scp_core_pos_to_scmi_channel(plat_my_core_pos(),
160 &domain_id, &channel_id);
161 ret = scmi_pwr_state_set(scmi_handles[channel_id],
162 domain_id, scmi_pwr_state);
163
164 if (ret != SCMI_E_SUCCESS) {
165 ERROR("SCMI set power state command return 0x%x unexpected\n",
166 ret);
167 panic();
168 }
169 #endif
170 }
171
172 /*
173 * Helper function to turn off a CPU power domain and its parent power domains
174 * if applicable.
175 */
css_scp_off(const struct psci_power_state * target_state)176 void css_scp_off(const struct psci_power_state *target_state)
177 {
178 unsigned int lvl = 0, channel_id, domain_id;
179 int ret;
180 uint32_t scmi_pwr_state = 0;
181
182 /* At-least the CPU level should be specified to be OFF */
183 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
184 ARM_LOCAL_STATE_OFF);
185
186 /* PSCI CPU OFF cannot be used to turn OFF system power domain */
187 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN);
188
189 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
190 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN)
191 break;
192
193 assert(target_state->pwr_domain_state[lvl] ==
194 ARM_LOCAL_STATE_OFF);
195 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl,
196 scmi_power_state_off);
197 }
198
199 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
200
201 css_scp_core_pos_to_scmi_channel(plat_my_core_pos(),
202 &domain_id, &channel_id);
203 ret = scmi_pwr_state_set(scmi_handles[channel_id],
204 domain_id, scmi_pwr_state);
205 if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
206 ERROR("SCMI set power state command return 0x%x unexpected\n",
207 ret);
208 panic();
209 }
210 }
211
212 /*
213 * Helper function to turn ON a CPU power domain and its parent power domains
214 * if applicable.
215 */
css_scp_on(u_register_t mpidr)216 void css_scp_on(u_register_t mpidr)
217 {
218 unsigned int lvl = 0, channel_id, core_pos, domain_id;
219 int ret;
220 uint32_t scmi_pwr_state = 0;
221
222 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
223 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl,
224 scmi_power_state_on);
225
226 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
227
228 core_pos = (unsigned int)plat_core_pos_by_mpidr(mpidr);
229 assert(core_pos < PLATFORM_CORE_COUNT);
230
231 css_scp_core_pos_to_scmi_channel(core_pos, &domain_id,
232 &channel_id);
233 ret = scmi_pwr_state_set(scmi_handles[channel_id],
234 domain_id, scmi_pwr_state);
235 if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
236 ERROR("SCMI set power state command return 0x%x unexpected\n",
237 ret);
238 panic();
239 }
240 }
241
242 /*
243 * Helper function to get the power state of a power domain node as reported
244 * by the SCP.
245 */
css_scp_get_power_state(u_register_t mpidr,unsigned int power_level)246 int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level)
247 {
248 int ret;
249 uint32_t scmi_pwr_state = 0, lvl_state;
250 unsigned int channel_id, cpu_idx, domain_id;
251
252 /* We don't support get power state at the system power domain level */
253 if ((power_level > PLAT_MAX_PWR_LVL) ||
254 (power_level == CSS_SYSTEM_PWR_DMN_LVL)) {
255 WARN("Invalid power level %u specified for SCMI get power state\n",
256 power_level);
257 return PSCI_E_INVALID_PARAMS;
258 }
259
260 cpu_idx = (unsigned int)plat_core_pos_by_mpidr(mpidr);
261 assert(cpu_idx < PLATFORM_CORE_COUNT);
262
263 css_scp_core_pos_to_scmi_channel(cpu_idx, &domain_id, &channel_id);
264 ret = scmi_pwr_state_get(scmi_handles[channel_id],
265 domain_id, &scmi_pwr_state);
266
267 if (ret != SCMI_E_SUCCESS) {
268 WARN("SCMI get power state command return 0x%x unexpected\n",
269 ret);
270 return PSCI_E_INVALID_PARAMS;
271 }
272
273 /*
274 * Find the maximum power level described in the get power state
275 * command. If it is less than the requested power level, then assume
276 * the requested power level is ON.
277 */
278 if (SCMI_GET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state) < power_level)
279 return HW_ON;
280
281 lvl_state = SCMI_GET_PWR_STATE_LVL(scmi_pwr_state, power_level);
282 if (lvl_state == scmi_power_state_on)
283 return HW_ON;
284
285 assert((lvl_state == scmi_power_state_off) ||
286 (lvl_state == scmi_power_state_sleep));
287 return HW_OFF;
288 }
289
290 /*
291 * Callback function to raise a SGI designated to trigger the CPU power down
292 * sequence on all the online secondary cores.
293 */
css_raise_pwr_down_interrupt(u_register_t mpidr)294 static void css_raise_pwr_down_interrupt(u_register_t mpidr)
295 {
296 #if CSS_SYSTEM_GRACEFUL_RESET
297 plat_ic_raise_el3_sgi(CSS_CPU_PWR_DOWN_REQ_INTR, mpidr);
298 #endif
299 }
300
css_scp_system_off(int state)301 void __dead2 css_scp_system_off(int state)
302 {
303 int ret;
304
305 /*
306 * Before issuing the system power down command, set the trusted mailbox
307 * to 0. This will ensure that in the case of a warm/cold reset, the
308 * primary CPU executes from the cold boot sequence.
309 */
310 mmio_write_64(PLAT_ARM_TRUSTED_MAILBOX_BASE, 0U);
311
312 /*
313 * Send powerdown request to online secondary core(s)
314 */
315 ret = psci_stop_other_cores(0, css_raise_pwr_down_interrupt);
316 if (ret != PSCI_E_SUCCESS) {
317 ERROR("Failed to powerdown secondary core(s)\n");
318 }
319
320 /*
321 * Disable GIC CPU interface to prevent pending interrupt from waking
322 * up the AP from WFI.
323 */
324 plat_arm_gic_cpuif_disable();
325 plat_arm_gic_redistif_off();
326
327 /*
328 * Issue SCMI command. First issue a graceful
329 * request and if that fails force the request.
330 */
331 ret = scmi_sys_pwr_state_set(scmi_handles[default_scmi_channel_id],
332 SCMI_SYS_PWR_FORCEFUL_REQ,
333 state);
334
335 if (ret != SCMI_E_SUCCESS) {
336 ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n",
337 state, ret);
338 panic();
339 }
340
341 /* Powerdown of primary core */
342 psci_pwrdown_cpu(PLAT_MAX_PWR_LVL);
343 wfi();
344 ERROR("CSS set power state: operation not handled.\n");
345 panic();
346 }
347
348 /*
349 * Helper function to shutdown the system via SCMI.
350 */
css_scp_sys_shutdown(void)351 void __dead2 css_scp_sys_shutdown(void)
352 {
353 css_scp_system_off(SCMI_SYS_PWR_SHUTDOWN);
354 }
355
356 /*
357 * Helper function to reset the system via SCMI.
358 */
css_scp_sys_reboot(void)359 void __dead2 css_scp_sys_reboot(void)
360 {
361 css_scp_system_off(SCMI_SYS_PWR_COLD_RESET);
362 }
363
scmi_ap_core_init(scmi_channel_t * ch)364 static int scmi_ap_core_init(scmi_channel_t *ch)
365 {
366 #if PROGRAMMABLE_RESET_ADDRESS
367 uint32_t version;
368 int ret;
369
370 ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version);
371 if (ret != SCMI_E_SUCCESS) {
372 WARN("SCMI AP core protocol version message failed\n");
373 return -1;
374 }
375
376 if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) {
377 WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n",
378 version, SCMI_AP_CORE_PROTO_VER);
379 return -1;
380 }
381 INFO("SCMI AP core protocol version 0x%x detected\n", version);
382 #endif
383 return 0;
384 }
385
plat_arm_pwrc_setup(void)386 void __init plat_arm_pwrc_setup(void)
387 {
388 unsigned int composite_id, idx;
389
390 for (idx = 0; idx < PLAT_ARM_SCMI_CHANNEL_COUNT; idx++) {
391 INFO("Initializing SCMI driver on channel %d\n", idx);
392
393 scmi_channels[idx].info = plat_css_get_scmi_info(idx);
394 scmi_channels[idx].lock = ARM_SCMI_LOCK_GET_INSTANCE;
395 scmi_handles[idx] = scmi_init(&scmi_channels[idx]);
396
397 if (scmi_handles[idx] == NULL) {
398 ERROR("SCMI Initialization failed on channel %d\n", idx);
399 panic();
400 }
401
402 if (scmi_ap_core_init(&scmi_channels[idx]) < 0) {
403 ERROR("SCMI AP core protocol initialization failed\n");
404 panic();
405 }
406 }
407
408 composite_id = plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()];
409 default_scmi_channel_id = GET_SCMI_CHANNEL_ID(composite_id);
410 }
411
412 /******************************************************************************
413 * This function overrides the default definition for ARM platforms. Initialize
414 * the SCMI driver, query capability via SCMI and modify the PSCI capability
415 * based on that.
416 *****************************************************************************/
css_scmi_override_pm_ops(plat_psci_ops_t * ops)417 const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops)
418 {
419 uint32_t msg_attr;
420 int ret;
421 void *scmi_handle = scmi_handles[default_scmi_channel_id];
422
423 assert(scmi_handle);
424
425 /* Check that power domain POWER_STATE_SET message is supported */
426 ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID,
427 SCMI_PWR_STATE_SET_MSG, &msg_attr);
428 if (ret != SCMI_E_SUCCESS) {
429 ERROR("Set power state command is not supported by SCMI\n");
430 panic();
431 }
432
433 /*
434 * Don't support PSCI NODE_HW_STATE call if SCMI doesn't support
435 * POWER_STATE_GET message.
436 */
437 ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID,
438 SCMI_PWR_STATE_GET_MSG, &msg_attr);
439 if (ret != SCMI_E_SUCCESS)
440 ops->get_node_hw_state = NULL;
441
442 /* Check if the SCMI SYSTEM_POWER_STATE_SET message is supported */
443 ret = scmi_proto_msg_attr(scmi_handle, SCMI_SYS_PWR_PROTO_ID,
444 SCMI_SYS_PWR_STATE_SET_MSG, &msg_attr);
445 if (ret != SCMI_E_SUCCESS) {
446 /* System power management operations are not supported */
447 ops->system_off = NULL;
448 ops->system_reset = NULL;
449 ops->get_sys_suspend_power_state = NULL;
450 } else {
451 if (!(msg_attr & SCMI_SYS_PWR_SUSPEND_SUPPORTED)) {
452 /*
453 * System power management protocol is available, but
454 * it does not support SYSTEM SUSPEND.
455 */
456 ops->get_sys_suspend_power_state = NULL;
457 }
458 if (!(msg_attr & SCMI_SYS_PWR_WARM_RESET_SUPPORTED)) {
459 /*
460 * WARM reset is not available.
461 */
462 ops->system_reset2 = NULL;
463 }
464 }
465
466 return ops;
467 }
468
css_system_reset2(int is_vendor,int reset_type,u_register_t cookie)469 int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
470 {
471 if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET))
472 return PSCI_E_INVALID_PARAMS;
473
474 css_scp_system_off(SCMI_SYS_PWR_WARM_RESET);
475 /*
476 * css_scp_system_off cannot return (it is a __dead function),
477 * but css_system_reset2 has to return some value, even in
478 * this case.
479 */
480 return 0;
481 }
482
483 #if PROGRAMMABLE_RESET_ADDRESS
plat_arm_program_trusted_mailbox(uintptr_t address)484 void plat_arm_program_trusted_mailbox(uintptr_t address)
485 {
486 int ret, i;
487
488 for (i = 0; i < PLAT_ARM_SCMI_CHANNEL_COUNT; i++) {
489 assert(scmi_handles[i]);
490
491 ret = scmi_ap_core_set_reset_addr(scmi_handles[i], address,
492 SCMI_AP_CORE_LOCK_ATTR);
493 if (ret != SCMI_E_SUCCESS) {
494 ERROR("CSS: Failed to program reset address: %d\n", ret);
495 panic();
496 }
497 }
498 }
499 #endif
500
