1/*
2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9#include <common/bl_common.ld.h>
10#include <lib/xlat_tables/xlat_tables_defs.h>
11
12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
13OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
14ENTRY(bl2u_entrypoint)
15
16MEMORY {
17    RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
18}
19
20SECTIONS {
21    RAM_REGION_START = ORIGIN(RAM);
22    RAM_REGION_LENGTH = LENGTH(RAM);
23    . = BL2U_BASE;
24
25    ASSERT(. == ALIGN(PAGE_SIZE),
26        "BL2U_BASE address is not aligned on a page boundary.")
27
28#if SEPARATE_CODE_AND_RODATA
29    .text . : {
30        __TEXT_START__ = .;
31
32        *bl2u_entrypoint.o(.text*)
33        *(SORT_BY_ALIGNMENT(.text*))
34        *(.vectors)
35        __TEXT_END_UNALIGNED__ = .;
36
37        . = ALIGN(PAGE_SIZE);
38
39        __TEXT_END__ = .;
40    } >RAM
41
42    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
43    .ARM.extab . : {
44        *(.ARM.extab* .gnu.linkonce.armextab.*)
45    } >RAM
46
47    .ARM.exidx . : {
48        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
49    } >RAM
50
51    .rodata . : {
52        __RODATA_START__ = .;
53        *(SORT_BY_ALIGNMENT(.rodata*))
54
55        RODATA_COMMON
56
57        __RODATA_END_UNALIGNED__ = .;
58        . = ALIGN(PAGE_SIZE);
59        __RODATA_END__ = .;
60    } >RAM
61#else /* SEPARATE_CODE_AND_RODATA */
62    .ro . : {
63        __RO_START__ = .;
64
65        *bl2u_entrypoint.o(.text*)
66        *(SORT_BY_ALIGNMENT(.text*))
67        *(SORT_BY_ALIGNMENT(.rodata*))
68
69        RODATA_COMMON
70
71        *(.vectors)
72
73        __RO_END_UNALIGNED__ = .;
74
75        /*
76         * Memory page(s) mapped to this section will be marked as read-only,
77         * executable. No RW data from the next section must creep in. Ensure
78         * that the rest of the current memory page is unused.
79         */
80        . = ALIGN(PAGE_SIZE);
81
82        __RO_END__ = .;
83    } >RAM
84#endif /* SEPARATE_CODE_AND_RODATA */
85
86    __RW_START__ = .;
87
88    DATA_SECTION >RAM
89    STACK_SECTION >RAM
90    BSS_SECTION >RAM
91    XLAT_TABLE_SECTION >RAM
92
93#if USE_COHERENT_MEM
94    /*
95     * The base address of the coherent memory section must be page-aligned to
96     * guarantee that the coherent data are stored on their own pages and are
97     * not mixed with normal data.  This is required to set up the correct
98     * memory attributes for the coherent data page tables.
99     */
100    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
101        __COHERENT_RAM_START__ = .;
102        *(.tzfw_coherent_mem)
103        __COHERENT_RAM_END_UNALIGNED__ = .;
104
105        /*
106         * Memory page(s) mapped to this section will be marked as device
107         * memory. No other unexpected data must creep in. Ensure the rest of
108         * the current memory page is unused.
109         */
110        . = ALIGN(PAGE_SIZE);
111
112        __COHERENT_RAM_END__ = .;
113    } >RAM
114#endif /* USE_COHERENT_MEM */
115
116    __RW_END__ = .;
117    __BL2U_END__ = .;
118
119    __BSS_SIZE__ = SIZEOF(.bss);
120
121    ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
122    RAM_REGION_END = .;
123}
124