1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * The .data section gets copied from ROM to RAM at runtime. Its LMA should be
9 * 16-byte aligned to allow efficient copying of 16-bytes aligned regions in it.
10 * Its VMA must be page-aligned as it marks the first read/write page.
11 */
12#define DATA_ALIGN	16
13
14#include <common/bl_common.ld.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
16
17OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
18OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
19ENTRY(bl1_entrypoint)
20
21MEMORY {
22    ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
23    RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
24}
25
26SECTIONS {
27    ROM_REGION_START = ORIGIN(ROM);
28    ROM_REGION_LENGTH = LENGTH(ROM);
29    RAM_REGION_START = ORIGIN(RAM);
30    RAM_REGION_LENGTH = LENGTH(RAM);
31
32    . = BL1_RO_BASE;
33
34    ASSERT(. == ALIGN(PAGE_SIZE),
35        "BL1_RO_BASE address is not aligned on a page boundary.")
36
37#if SEPARATE_CODE_AND_RODATA
38    .text . : {
39        __TEXT_START__ = .;
40
41        *bl1_entrypoint.o(.text*)
42        *(SORT_BY_ALIGNMENT(.text*))
43        *(.vectors)
44        __TEXT_END_UNALIGNED__ = .;
45
46        . = ALIGN(PAGE_SIZE);
47
48        __TEXT_END__ = .;
49    } >ROM
50
51    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
52    .ARM.extab . : {
53        *(.ARM.extab* .gnu.linkonce.armextab.*)
54    } >ROM
55
56    .ARM.exidx . : {
57        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
58    } >ROM
59
60    .rodata . : {
61        __RODATA_START__ = .;
62
63        *(SORT_BY_ALIGNMENT(.rodata*))
64
65        RODATA_COMMON
66
67        /*
68         * No need to pad out the .rodata section to a page boundary. Next is
69         * the .data section, which can mapped in ROM with the same memory
70         * attributes as the .rodata section.
71         *
72         * Pad out to 16 bytes though as .data section needs to be 16-byte
73         * aligned and lld does not align the LMA to the alignment specified
74         * on the .data section.
75         */
76        __RODATA_END_UNALIGNED__ = .;
77        __RODATA_END__ = .;
78
79        . = ALIGN(16);
80    } >ROM
81#else /* SEPARATE_CODE_AND_RODATA */
82    .ro . : {
83        __RO_START__ = .;
84
85        *bl1_entrypoint.o(.text*)
86        *(SORT_BY_ALIGNMENT(.text*))
87        *(SORT_BY_ALIGNMENT(.rodata*))
88
89        RODATA_COMMON
90
91        *(.vectors)
92
93        __RO_END__ = .;
94
95        /*
96         * Pad out to 16 bytes as the .data section needs to be 16-byte aligned
97         * and lld does not align the LMA to the alignment specified on the
98         * .data section.
99         */
100        . = ALIGN(16);
101    } >ROM
102#endif /* SEPARATE_CODE_AND_RODATA */
103
104    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
105        "cpu_ops not defined for this platform.")
106
107    ROM_REGION_END = .;
108    . = BL1_RW_BASE;
109
110    ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
111        "BL1_RW_BASE address is not aligned on a page boundary.")
112
113    DATA_SECTION >RAM AT>ROM
114
115    __DATA_RAM_START__ = __DATA_START__;
116    __DATA_RAM_END__ = __DATA_END__;
117
118    STACK_SECTION >RAM
119    BSS_SECTION >RAM
120    XLAT_TABLE_SECTION >RAM
121
122#if USE_COHERENT_MEM
123    /*
124     * The base address of the coherent memory section must be page-aligned to
125     * guarantee that the coherent data are stored on their own pages and are
126     * not mixed with normal data. This is required to set up the correct memory
127     * attributes for the coherent data page tables.
128     */
129    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
130        __COHERENT_RAM_START__ = .;
131        *(.tzfw_coherent_mem)
132        __COHERENT_RAM_END_UNALIGNED__ = .;
133
134        /*
135         * Memory page(s) mapped to this section will be marked as device
136         * memory. No other unexpected data must creep in. Ensure the rest of
137         * the current memory page is unused.
138         */
139        . = ALIGN(PAGE_SIZE);
140
141        __COHERENT_RAM_END__ = .;
142    } >RAM
143#endif /* USE_COHERENT_MEM */
144
145    __BL1_RAM_START__ = ADDR(.data);
146    __BL1_RAM_END__ = .;
147
148    __DATA_ROM_START__ = LOADADDR(.data);
149    __DATA_SIZE__ = SIZEOF(.data);
150
151    /*
152     * The .data section is the last PROGBITS section so its end marks the end
153     * of BL1's actual content in Trusted ROM.
154     */
155    __BL1_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
156
157    ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
158        "BL1's ROM content has exceeded its limit.")
159
160    __BSS_SIZE__ = SIZEOF(.bss);
161
162#if USE_COHERENT_MEM
163    __COHERENT_RAM_UNALIGNED_SIZE__ =
164        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
165#endif /* USE_COHERENT_MEM */
166
167    ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
168    RAM_REGION_END = .;
169}
170