1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2019-2020, Linaro Limited and Contributors. 4 * All rights reserved. 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <tbbr_img_def.h> 13 14 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16 17 #define PLATFORM_STACK_SIZE 0x1000 18 19 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 20 /* 21 * Define the number of cores per cluster used in calculating core position. 22 * The cluster number is shifted by this value and added to the core ID, 23 * so its value represents log2(cores/cluster). 24 * Default is 2**(3) = 8 cores per cluster. 25 */ 26 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(3) 27 #define PLATFORM_CLUSTER_COUNT U(64) 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 29 PLATFORM_MAX_CPUS_PER_CLUSTER) 30 #define QEMU_PRIMARY_CPU U(0) 31 32 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 33 PLATFORM_CORE_COUNT) 34 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 35 36 #define PLAT_MAX_RET_STATE 1 37 #define PLAT_MAX_OFF_STATE 2 38 39 /* Local power state for power domains in Run state. */ 40 #define PLAT_LOCAL_STATE_RUN 0 41 /* Local power state for retention. Valid only for CPU power domains */ 42 #define PLAT_LOCAL_STATE_RET 1 43 /* 44 * Local power state for OFF/power-down. Valid for CPU and cluster power 45 * domains. 46 */ 47 #define PLAT_LOCAL_STATE_OFF 2 48 49 /* 50 * Macros used to parse state information from State-ID if it is using the 51 * recommended encoding for State-ID. 52 */ 53 #define PLAT_LOCAL_PSTATE_WIDTH 4 54 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 55 56 /* 57 * Some data must be aligned on the biggest cache line size in the platform. 58 * This is known only to the platform as it might have a combination of 59 * integrated and external caches. 60 */ 61 #define CACHE_WRITEBACK_SHIFT 6 62 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 63 64 /* 65 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 66 * and secure DRAM. 67 */ 68 #define SEC_ROM_BASE 0x00000000 69 #define SEC_ROM_SIZE 0x00020000 70 71 #define NS_DRAM0_BASE 0x10000000000ULL 72 #define NS_DRAM0_SIZE 0x00020000000 73 74 #define SEC_SRAM_BASE 0x20000000 75 #define SEC_SRAM_SIZE 0x20000000 76 77 /* 78 * RAD just placeholders, need to be chosen after finalizing mem map 79 */ 80 #define SEC_DRAM_BASE 0x1000 81 #define SEC_DRAM_SIZE 0x1000 82 83 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 84 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 85 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 86 87 /* 88 * ARM-TF lives in SRAM, partition it here 89 */ 90 91 #define SHARED_RAM_BASE SEC_SRAM_BASE 92 #define SHARED_RAM_SIZE 0x00002000 93 94 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 95 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 96 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 97 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 98 PLAT_QEMU_HOLD_ENTRY_SIZE) 99 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 100 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 101 #define PLAT_QEMU_HOLD_STATE_WAIT 0 102 #define PLAT_QEMU_HOLD_STATE_GO 1 103 104 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 105 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 106 107 /* 108 * BL1 specific defines. 109 * 110 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 111 * addresses. 112 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 113 * the current BL1 RW debug size plus a little space for growth. 114 */ 115 #define BL1_SIZE 0x12000 116 #define BL1_RO_BASE SEC_ROM_BASE 117 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 118 #define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE) 119 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 120 121 /* 122 * BL2 specific defines. 123 * 124 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 125 * size plus a little space for growth. 126 */ 127 #define BL2_SIZE 0x1D000 128 #define BL2_BASE (BL31_BASE - BL2_SIZE) 129 #define BL2_LIMIT BL31_BASE 130 131 /* 132 * BL3-1 specific defines. 133 * 134 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 135 * current BL3-1 debug size plus a little space for growth. 136 */ 137 #define BL31_SIZE 0x300000 138 #define BL31_BASE (BL31_LIMIT - BL31_SIZE) 139 #define BL31_LIMIT (BL1_RW_BASE) 140 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 141 142 143 /* 144 * BL3-2 specific defines. 145 * 146 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 147 */ 148 #define BL32_SRAM_BASE BL_RAM_BASE 149 #define BL32_SRAM_LIMIT BL2_BASE 150 151 #define BL32_MEM_BASE BL_RAM_BASE 152 #define BL32_MEM_SIZE (BL_RAM_SIZE - BL1_SIZE - \ 153 BL2_SIZE - BL31_SIZE) 154 #define BL32_BASE BL32_SRAM_BASE 155 #define BL32_LIMIT BL32_SRAM_LIMIT 156 157 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 158 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 159 160 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42) 161 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42) 162 #if SPM_MM 163 #define MAX_MMAP_REGIONS 12 164 #define MAX_XLAT_TABLES 12 165 #else 166 #define MAX_MMAP_REGIONS 11 167 #define MAX_XLAT_TABLES 11 168 #endif 169 #define MAX_IO_DEVICES 3 170 #define MAX_IO_HANDLES 4 171 172 #if SPM_MM && defined(IMAGE_BL31) 173 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 174 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 50 175 #endif 176 177 /* 178 * PL011 related constants 179 */ 180 #define UART0_BASE 0x60000000 181 #define UART1_BASE 0x60030000 182 #define UART0_CLK_IN_HZ 1 183 #define UART1_CLK_IN_HZ 1 184 185 /* Secure UART */ 186 #define UART2_BASE 0x60040000 187 #define UART2_CLK_IN_HZ 1 188 189 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 190 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 191 192 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 193 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 194 195 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 196 197 #define QEMU_FLASH0_BASE 0x00000000 198 #define QEMU_FLASH0_SIZE 0x10000000 199 #define QEMU_FLASH1_BASE 0x10000000 200 #define QEMU_FLASH1_SIZE 0x10000000 201 202 #define PLAT_QEMU_FIP_BASE 0x00008000 203 #define PLAT_QEMU_FIP_MAX_SIZE 0x00400000 204 205 /* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */ 206 #define DEVICE0_BASE 0x40000000 207 #define DEVICE0_SIZE 0x04080000 208 /* This is map from NORMAL_UART up to SECURE_UART_MM */ 209 #define DEVICE1_BASE 0x60000000 210 #define DEVICE1_SIZE 0x10041000 211 /* This is a map for SECURE_EC */ 212 #define DEVICE2_BASE 0x50000000 213 #define DEVICE2_SIZE 0x00001000 214 215 /* 216 * GIC related constants 217 * We use GICv3 where CPU Interface registers are not memory mapped 218 */ 219 #define GICD_BASE 0x40060000 220 #define GICR_BASE 0x40080000 221 #define GICC_BASE 0x0 222 223 #define QEMU_IRQ_SEC_SGI_0 8 224 #define QEMU_IRQ_SEC_SGI_1 9 225 #define QEMU_IRQ_SEC_SGI_2 10 226 #define QEMU_IRQ_SEC_SGI_3 11 227 #define QEMU_IRQ_SEC_SGI_4 12 228 #define QEMU_IRQ_SEC_SGI_5 13 229 #define QEMU_IRQ_SEC_SGI_6 14 230 #define QEMU_IRQ_SEC_SGI_7 15 231 232 /****************************************************************************** 233 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 234 * interrupts. 235 *****************************************************************************/ 236 #define PLATFORM_G1S_PROPS(grp) \ 237 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 238 grp, GIC_INTR_CFG_EDGE), \ 239 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 240 grp, GIC_INTR_CFG_EDGE), \ 241 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 242 grp, GIC_INTR_CFG_EDGE), \ 243 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 244 grp, GIC_INTR_CFG_EDGE), \ 245 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 246 grp, GIC_INTR_CFG_EDGE), \ 247 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 248 grp, GIC_INTR_CFG_EDGE), \ 249 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 250 grp, GIC_INTR_CFG_EDGE), \ 251 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 252 grp, GIC_INTR_CFG_EDGE) 253 254 #define PLATFORM_G0_PROPS(grp) 255 256 /* 257 * DT related constants 258 */ 259 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 260 #define PLAT_QEMU_DT_MAX_SIZE 0x100000 261 262 /* 263 * System counter 264 */ 265 #define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) 266 267 #if SPM_MM 268 #define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE 269 #define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000) 270 271 #ifdef IMAGE_BL2 272 /* In BL2 all memory allocated to the SPM Payload image is marked as RW. */ 273 # define QEMU_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 274 PLAT_QEMU_SP_IMAGE_BASE, \ 275 PLAT_QEMU_SP_IMAGE_SIZE, \ 276 MT_MEMORY | MT_RW | \ 277 MT_SECURE) 278 #elif IMAGE_BL31 279 /* All SPM Payload memory is marked as code in S-EL0 */ 280 # define QEMU_SP_IMAGE_MMAP MAP_REGION2(PLAT_QEMU_SP_IMAGE_BASE, \ 281 PLAT_QEMU_SP_IMAGE_BASE, \ 282 PLAT_QEMU_SP_IMAGE_SIZE, \ 283 MT_CODE | MT_SECURE | \ 284 MT_USER, \ 285 PAGE_SIZE) 286 #endif 287 288 /* 289 * EL3 -> S-EL0 secure shared memory 290 */ 291 #define PLAT_SPM_BUF_PCPU_SIZE ULL(0x10000) 292 #define PLAT_SPM_BUF_SIZE (PLATFORM_CORE_COUNT * \ 293 PLAT_SPM_BUF_PCPU_SIZE) 294 #define PLAT_SPM_BUF_BASE (BL32_LIMIT - PLAT_SPM_BUF_SIZE) 295 296 #define QEMU_SPM_BUF_EL3_MMAP MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, \ 297 PLAT_SPM_BUF_SIZE, \ 298 MT_RW_DATA | MT_SECURE) 299 300 #define QEMU_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \ 301 PLAT_SPM_BUF_BASE, \ 302 PLAT_SPM_BUF_SIZE, \ 303 MT_RO_DATA | MT_SECURE | \ 304 MT_USER, \ 305 PAGE_SIZE) 306 307 /* 308 * Shared memory between Normal world and S-EL0 for 309 * passing data during service requests. It will be marked as RW and NS. 310 * This buffer is allocated at the top of NS_DRAM, the base address is 311 * overridden in SPM initialization. 312 */ 313 #define PLAT_QEMU_SP_IMAGE_NS_BUF_BASE (PLAT_QEMU_DT_BASE + \ 314 PLAT_QEMU_DT_MAX_SIZE) 315 #define PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE ULL(0x200000) 316 317 #define QEMU_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 318 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 319 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 320 PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE, \ 321 MT_RW_DATA | MT_NS | \ 322 MT_USER, \ 323 PAGE_SIZE) 324 325 #define PLAT_SP_IMAGE_NS_BUF_BASE PLAT_QEMU_SP_IMAGE_NS_BUF_BASE 326 #define PLAT_SP_IMAGE_NS_BUF_SIZE PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE 327 328 #define PLAT_QEMU_SP_IMAGE_HEAP_BASE (PLAT_QEMU_SP_IMAGE_BASE + \ 329 PLAT_QEMU_SP_IMAGE_SIZE) 330 #define PLAT_QEMU_SP_IMAGE_HEAP_SIZE ULL(0x800000) 331 332 #define PLAT_SP_IMAGE_STACK_BASE (PLAT_QEMU_SP_IMAGE_HEAP_BASE + \ 333 PLAT_QEMU_SP_IMAGE_HEAP_SIZE) 334 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000) 335 #define QEMU_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 336 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 337 338 #define QEMU_SP_IMAGE_RW_MMAP MAP_REGION2( \ 339 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 340 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 341 (QEMU_SP_IMAGE_STACK_TOTAL_SIZE + \ 342 PLAT_QEMU_SP_IMAGE_HEAP_SIZE), \ 343 MT_RW_DATA | MT_SECURE | \ 344 MT_USER, \ 345 PAGE_SIZE) 346 347 /* 348 * Secure variable storage is located at Secure Flash. 349 */ 350 #if SPM_MM 351 #define QEMU_SECURE_VARSTORE_BASE 0x01000000 352 #define QEMU_SECURE_VARSTORE_SIZE 0x00100000 353 #define MAP_SECURE_VARSTORE MAP_REGION_FLAT( \ 354 QEMU_SECURE_VARSTORE_BASE, \ 355 QEMU_SECURE_VARSTORE_SIZE, \ 356 MT_DEVICE | MT_RW | \ 357 MT_SECURE | MT_USER) 358 #endif 359 360 /* Total number of memory regions with distinct properties */ 361 #define PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS 6 362 363 /* 364 * Name of the section to put the translation tables used by the S-EL1/S-EL0 365 * context of a Secure Partition. 366 */ 367 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" 368 #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" 369 370 /* Cookies passed to the Secure Partition at boot. Not used by QEMU platforms.*/ 371 #define PLAT_SPM_COOKIE_0 ULL(0) 372 #define PLAT_SPM_COOKIE_1 ULL(0) 373 #endif 374 375 #define QEMU_PRI_BITS 2 376 #define PLAT_SP_PRI 0x20 377 378 #endif /* PLATFORM_DEF_H */ 379
