1 /* 2 * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /**************************************************************** 8 * Auto generated by DE, please DO NOT modify this file directly. 9 *****************************************************************/ 10 #ifndef MT_SPM_REG 11 #define MT_SPM_REG 12 13 #include "pcm_def.h" 14 #include <platform_def.h> 15 #include "sleep_def.h" 16 17 /************************************** 18 * Define and Declare 19 **************************************/ 20 #define POWERON_CONFIG_EN (SPM_BASE + 0x000) 21 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) 22 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) 23 #define SPM_CLK_CON (SPM_BASE + 0x00C) 24 #define SPM_CLK_SETTLE (SPM_BASE + 0x010) 25 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) 26 #define PCM_CON0 (SPM_BASE + 0x018) 27 #define PCM_CON1 (SPM_BASE + 0x01C) 28 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020) 29 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024) 30 #define PCM_REG_DATA_INI (SPM_BASE + 0x028) 31 #define PCM_PWR_IO_EN (SPM_BASE + 0x02C) 32 #define PCM_TIMER_VAL (SPM_BASE + 0x030) 33 #define PCM_WDT_VAL (SPM_BASE + 0x034) 34 #define SPM_SRC6_MASK (SPM_BASE + 0x038) 35 #define SPM_SW_RST_CON (SPM_BASE + 0x040) 36 #define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) 37 #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) 38 #define VS1_PSR_MASK_B (SPM_BASE + 0x04C) 39 #define VS2_PSR_MASK_B (SPM_BASE + 0x050) 40 #define MD32_CLK_CON (SPM_BASE + 0x084) 41 #define SPM_SRAM_RSV_CON (SPM_BASE + 0x088) 42 #define SPM_SWINT (SPM_BASE + 0x08C) 43 #define SPM_SWINT_SET (SPM_BASE + 0x090) 44 #define SPM_SWINT_CLR (SPM_BASE + 0x094) 45 #define SPM_SCP_MAILBOX (SPM_BASE + 0x098) 46 #define SCP_SPM_MAILBOX (SPM_BASE + 0x09C) 47 #define SPM_TWAM_CON (SPM_BASE + 0x0A0) 48 #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) 49 #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) 50 #define SPM_SCP_IRQ (SPM_BASE + 0x0AC) 51 #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) 52 #define SPM_IRQ_MASK (SPM_BASE + 0x0B4) 53 #define SPM_SRC_REQ (SPM_BASE + 0x0B8) 54 #define SPM_SRC_MASK (SPM_BASE + 0x0BC) 55 #define SPM_SRC2_MASK (SPM_BASE + 0x0C0) 56 #define SPM_SRC3_MASK (SPM_BASE + 0x0C4) 57 #define SPM_SRC4_MASK (SPM_BASE + 0x0C8) 58 #define SPM_SRC5_MASK (SPM_BASE + 0x0CC) 59 #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0D0) 60 #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0D4) 61 #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0D8) 62 #define SCP_CLK_CON (SPM_BASE + 0x0DC) 63 #define PCM_DEBUG_CON (SPM_BASE + 0x0E0) 64 #define AHB_BUS_CON (SPM_BASE + 0x0E4) 65 #define DDR_EN_DBC_CON0 (SPM_BASE + 0x0E8) 66 #define DDR_EN_DBC_CON1 (SPM_BASE + 0x0EC) 67 #define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0F0) 68 #define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0F4) 69 #define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0F8) 70 #define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0FC) 71 #define PCM_REG0_DATA (SPM_BASE + 0x100) 72 #define PCM_REG2_DATA (SPM_BASE + 0x104) 73 #define PCM_REG6_DATA (SPM_BASE + 0x108) 74 #define PCM_REG7_DATA (SPM_BASE + 0x10C) 75 #define PCM_REG13_DATA (SPM_BASE + 0x110) 76 #define SRC_REQ_STA_0 (SPM_BASE + 0x114) 77 #define SRC_REQ_STA_1 (SPM_BASE + 0x118) 78 #define SRC_REQ_STA_2 (SPM_BASE + 0x11C) 79 #define PCM_TIMER_OUT (SPM_BASE + 0x120) 80 #define PCM_WDT_OUT (SPM_BASE + 0x124) 81 #define SPM_IRQ_STA (SPM_BASE + 0x128) 82 #define SRC_REQ_STA_4 (SPM_BASE + 0x12C) 83 #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x130) 84 #define MD32PCM_EVENT_STA (SPM_BASE + 0x134) 85 #define SPM_WAKEUP_STA (SPM_BASE + 0x138) 86 #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x13C) 87 #define SPM_WAKEUP_MISC (SPM_BASE + 0x140) 88 #define MM_DVFS_HALT (SPM_BASE + 0x144) 89 #define BUS_PROTECT_RDY (SPM_BASE + 0x150) 90 #define BUS_PROTECT1_RDY (SPM_BASE + 0x154) 91 #define BUS_PROTECT2_RDY (SPM_BASE + 0x158) 92 #define BUS_PROTECT3_RDY (SPM_BASE + 0x15C) 93 #define SUBSYS_IDLE_STA (SPM_BASE + 0x160) 94 #define PCM_STA (SPM_BASE + 0x164) 95 #define SRC_REQ_STA_3 (SPM_BASE + 0x168) 96 #define PWR_STATUS (SPM_BASE + 0x16C) 97 #define PWR_STATUS_2ND (SPM_BASE + 0x170) 98 #define CPU_PWR_STATUS (SPM_BASE + 0x174) 99 #define OTHER_PWR_STATUS (SPM_BASE + 0x178) 100 #define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C) 101 #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180) 102 #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184) 103 #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188) 104 #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C) 105 #define MD32PCM_STA (SPM_BASE + 0x190) 106 #define MD32PCM_PC (SPM_BASE + 0x194) 107 #define DVFSRC_EVENT_STA (SPM_BASE + 0x1A4) 108 #define BUS_PROTECT4_RDY (SPM_BASE + 0x1A8) 109 #define BUS_PROTECT5_RDY (SPM_BASE + 0x1AC) 110 #define BUS_PROTECT6_RDY (SPM_BASE + 0x1B0) 111 #define BUS_PROTECT7_RDY (SPM_BASE + 0x1B4) 112 #define BUS_PROTECT8_RDY (SPM_BASE + 0x1B8) 113 #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0) 114 #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4) 115 #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8) 116 #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC) 117 #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0) 118 #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4) 119 #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8) 120 #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC) 121 #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0) 122 #define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4) 123 #define SPM_DVFS_STA (SPM_BASE + 0x1F8) 124 #define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC) 125 #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x200) 126 #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x204) 127 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x208) 128 #define SPM_CPU1_PWR_CON (SPM_BASE + 0x20C) 129 #define SPM_CPU2_PWR_CON (SPM_BASE + 0x210) 130 #define SPM_CPU3_PWR_CON (SPM_BASE + 0x214) 131 #define SPM_CPU4_PWR_CON (SPM_BASE + 0x218) 132 #define SPM_CPU5_PWR_CON (SPM_BASE + 0x21C) 133 #define SPM_CPU6_PWR_CON (SPM_BASE + 0x220) 134 #define SPM_CPU7_PWR_CON (SPM_BASE + 0x224) 135 #define ARMPLL_CLK_CON (SPM_BASE + 0x22C) 136 #define MCUSYS_IDLE_STA (SPM_BASE + 0x230) 137 #define GIC_WAKEUP_STA (SPM_BASE + 0x234) 138 #define CPU_SPARE_CON (SPM_BASE + 0x238) 139 #define CPU_SPARE_CON_SET (SPM_BASE + 0x23C) 140 #define CPU_SPARE_CON_CLR (SPM_BASE + 0x240) 141 #define ARMPLL_CLK_SEL (SPM_BASE + 0x244) 142 #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248) 143 #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C) 144 #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250) 145 #define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x260) 146 #define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x264) 147 #define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x268) 148 #define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x26C) 149 #define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x270) 150 #define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x274) 151 #define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x278) 152 #define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x27C) 153 #define MP0_CPU0_WFI_EN (SPM_BASE + 0x280) 154 #define MP0_CPU1_WFI_EN (SPM_BASE + 0x284) 155 #define MP0_CPU2_WFI_EN (SPM_BASE + 0x288) 156 #define MP0_CPU3_WFI_EN (SPM_BASE + 0x28C) 157 #define MP0_CPU4_WFI_EN (SPM_BASE + 0x290) 158 #define MP0_CPU5_WFI_EN (SPM_BASE + 0x294) 159 #define MP0_CPU6_WFI_EN (SPM_BASE + 0x298) 160 #define MP0_CPU7_WFI_EN (SPM_BASE + 0x29C) 161 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) 162 #define ROOT_CORE_ADDR (SPM_BASE + 0x2A4) 163 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) 164 #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4) 165 #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8) 166 #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC) 167 #define SW2SPM_INT (SPM_BASE + 0x2E0) 168 #define SW2SPM_INT_SET (SPM_BASE + 0x2E4) 169 #define SW2SPM_INT_CLR (SPM_BASE + 0x2E8) 170 #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC) 171 #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0) 172 #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4) 173 #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8) 174 #define SW2SPM_CFG (SPM_BASE + 0x2FC) 175 #define MD1_PWR_CON (SPM_BASE + 0x300) 176 #define CONN_PWR_CON (SPM_BASE + 0x304) 177 #define MFG0_PWR_CON (SPM_BASE + 0x308) 178 #define MFG1_PWR_CON (SPM_BASE + 0x30C) 179 #define MFG2_PWR_CON (SPM_BASE + 0x310) 180 #define MFG3_PWR_CON (SPM_BASE + 0x314) 181 #define MFG4_PWR_CON (SPM_BASE + 0x318) 182 #define MFG5_PWR_CON (SPM_BASE + 0x31C) 183 #define MFG6_PWR_CON (SPM_BASE + 0x320) 184 #define IFR_PWR_CON (SPM_BASE + 0x324) 185 #define IFR_SUB_PWR_CON (SPM_BASE + 0x328) 186 #define DPY_PWR_CON (SPM_BASE + 0x32C) 187 #define ISP_PWR_CON (SPM_BASE + 0x330) 188 #define ISP2_PWR_CON (SPM_BASE + 0x334) 189 #define IPE_PWR_CON (SPM_BASE + 0x338) 190 #define VDE_PWR_CON (SPM_BASE + 0x33C) 191 #define VDE2_PWR_CON (SPM_BASE + 0x340) 192 #define VEN_PWR_CON (SPM_BASE + 0x344) 193 #define VEN_CORE1_PWR_CON (SPM_BASE + 0x348) 194 #define MDP_PWR_CON (SPM_BASE + 0x34C) 195 #define DIS_PWR_CON (SPM_BASE + 0x350) 196 #define AUDIO_PWR_CON (SPM_BASE + 0x354) 197 #define ADSP_PWR_CON (SPM_BASE + 0x358) 198 #define CAM_PWR_CON (SPM_BASE + 0x35C) 199 #define CAM_RAWA_PWR_CON (SPM_BASE + 0x360) 200 #define CAM_RAWB_PWR_CON (SPM_BASE + 0x364) 201 #define CAM_RAWC_PWR_CON (SPM_BASE + 0x368) 202 #define SYSRAM_CON (SPM_BASE + 0x36C) 203 #define SYSROM_CON (SPM_BASE + 0x370) 204 #define SSPM_SRAM_CON (SPM_BASE + 0x374) 205 #define SCP_SRAM_CON (SPM_BASE + 0x378) 206 #define DPY_SHU_SRAM_CON (SPM_BASE + 0x37C) 207 #define UFS_SRAM_CON (SPM_BASE + 0x380) 208 #define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x384) 209 #define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x388) 210 #define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x38C) 211 #define USB_SRAM_CON (SPM_BASE + 0x390) 212 #define DUMMY_SRAM_CON (SPM_BASE + 0x394) 213 #define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x398) 214 #define EXT_BUCK_ISO (SPM_BASE + 0x39C) 215 #define DXCC_SRAM_CON (SPM_BASE + 0x3A0) 216 #define MSDC_SRAM_CON (SPM_BASE + 0x3A4) 217 #define DEBUGTOP_SRAM_CON (SPM_BASE + 0x3A8) 218 #define DP_TX_PWR_CON (SPM_BASE + 0x3AC) 219 #define DPMAIF_SRAM_CON (SPM_BASE + 0x3B0) 220 #define DPY_SHU2_SRAM_CON (SPM_BASE + 0x3B4) 221 #define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x3B8) 222 #define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x3BC) 223 #define MCUPM_SRAM_CON (SPM_BASE + 0x3C0) 224 #define DPY2_PWR_CON (SPM_BASE + 0x3C4) 225 #define PERI_PWR_CON (SPM_BASE + 0x3C8) 226 #define SPM_MEM_CK_SEL (SPM_BASE + 0x400) 227 #define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404) 228 #define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408) 229 #define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C) 230 #define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410) 231 #define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414) 232 #define SPM_EMI_BW_MODE (SPM_BASE + 0x418) 233 #define AP2MD_PEER_WAKEUP (SPM_BASE + 0x41C) 234 #define ULPOSC_CON (SPM_BASE + 0x420) 235 #define SPM2MM_CON (SPM_BASE + 0x424) 236 #define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x428) 237 #define SPM2MCUPM_CON (SPM_BASE + 0x42C) 238 #define AP_MDSRC_REQ (SPM_BASE + 0x430) 239 #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x434) 240 #define SPM2MD_DVFS_CON (SPM_BASE + 0x438) 241 #define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) 242 #define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x440) 243 #define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x444) 244 #define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x448) 245 #define SPM_PLL_CON (SPM_BASE + 0x44C) 246 #define CPU_DVFS_REQ (SPM_BASE + 0x450) 247 #define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x454) 248 #define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x458) 249 #define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x45C) 250 #define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x460) 251 #define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x464) 252 #define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x468) 253 #define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x46C) 254 #define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x470) 255 #define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x474) 256 #define RELAY_DVFS_LEVEL (SPM_BASE + 0x478) 257 #define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x480) 258 #define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x484) 259 #define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x488) 260 #define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x48C) 261 #define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x490) 262 #define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x494) 263 #define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x498) 264 #define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x49C) 265 #define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x4A0) 266 #define SPM_DVFS_LEVEL (SPM_BASE + 0x4A4) 267 #define SPM_CIRQ_CON (SPM_BASE + 0x4A8) 268 #define SPM_DVFS_MISC (SPM_BASE + 0x4AC) 269 #define SPM_VS1_VS2_RC_CON (SPM_BASE + 0x4B0) 270 #define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4B4) 271 #define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4B8) 272 #define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4BC) 273 #define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4C0) 274 #define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4C4) 275 #define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4C8) 276 #define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4CC) 277 #define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4D0) 278 #define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4D4) 279 #define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4D8) 280 #define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4DC) 281 #define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4E0) 282 #define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4E4) 283 #define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4E8) 284 #define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4EC) 285 #define SPM_CG_CHECK_CON (SPM_BASE + 0x4F0) 286 #define SPM_SRC_RDY_STA (SPM_BASE + 0x4F4) 287 #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4F8) 288 #define SPM_FORCE_DVFS (SPM_BASE + 0x4FC) 289 #define SRCLKEN_RC_CFG (SPM_BASE + 0x500) 290 #define RC_CENTRAL_CFG1 (SPM_BASE + 0x504) 291 #define RC_CENTRAL_CFG2 (SPM_BASE + 0x508) 292 #define RC_CMD_ARB_CFG (SPM_BASE + 0x50C) 293 #define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x510) 294 #define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x514) 295 #define RC_DCXO_FPM_CFG (SPM_BASE + 0x518) 296 #define RC_CENTRAL_CFG3 (SPM_BASE + 0x51C) 297 #define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520) 298 #define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x524) 299 #define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x528) 300 #define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x52C) 301 #define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x530) 302 #define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x534) 303 #define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x538) 304 #define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x53C) 305 #define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x540) 306 #define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x544) 307 #define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x548) 308 #define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x54C) 309 #define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x550) 310 #define RC_SRCLKEN_SW_CON_CFG (SPM_BASE + 0x554) 311 #define RC_CENTRAL_CFG4 (SPM_BASE + 0x558) 312 #define RC_PROTOCOL_CHK_CFG (SPM_BASE + 0x560) 313 #define RC_DEBUG_CFG (SPM_BASE + 0x564) 314 #define RC_MISC_0 (SPM_BASE + 0x5B4) 315 #define RC_SPM_CTRL (SPM_BASE + 0x5B8) 316 #define SUBSYS_INTF_CFG (SPM_BASE + 0x5BC) 317 #define PCM_WDT_LATCH_25 (SPM_BASE + 0x5C0) 318 #define PCM_WDT_LATCH_26 (SPM_BASE + 0x5C4) 319 #define PCM_WDT_LATCH_27 (SPM_BASE + 0x5C8) 320 #define PCM_WDT_LATCH_28 (SPM_BASE + 0x5CC) 321 #define PCM_WDT_LATCH_29 (SPM_BASE + 0x5D0) 322 #define PCM_WDT_LATCH_30 (SPM_BASE + 0x5D4) 323 #define PCM_WDT_LATCH_31 (SPM_BASE + 0x5D8) 324 #define PCM_WDT_LATCH_32 (SPM_BASE + 0x5DC) 325 #define PCM_WDT_LATCH_33 (SPM_BASE + 0x5E0) 326 #define PCM_WDT_LATCH_34 (SPM_BASE + 0x5E4) 327 #define PCM_WDT_LATCH_35 (SPM_BASE + 0x5EC) 328 #define PCM_WDT_LATCH_36 (SPM_BASE + 0x5F0) 329 #define PCM_WDT_LATCH_37 (SPM_BASE + 0x5F4) 330 #define PCM_WDT_LATCH_38 (SPM_BASE + 0x5F8) 331 #define PCM_WDT_LATCH_39 (SPM_BASE + 0x5FC) 332 #define SPM_SW_FLAG_0 (SPM_BASE + 0x600) 333 #define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) 334 #define SPM_SW_FLAG_1 (SPM_BASE + 0x608) 335 #define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) 336 #define SPM_SW_RSV_0 (SPM_BASE + 0x610) 337 #define SPM_SW_RSV_1 (SPM_BASE + 0x614) 338 #define SPM_SW_RSV_2 (SPM_BASE + 0x618) 339 #define SPM_SW_RSV_3 (SPM_BASE + 0x61C) 340 #define SPM_SW_RSV_4 (SPM_BASE + 0x620) 341 #define SPM_SW_RSV_5 (SPM_BASE + 0x624) 342 #define SPM_SW_RSV_6 (SPM_BASE + 0x628) 343 #define SPM_SW_RSV_7 (SPM_BASE + 0x62C) 344 #define SPM_SW_RSV_8 (SPM_BASE + 0x630) 345 #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) 346 #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) 347 #define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) 348 #define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) 349 #define SPM_RSV_CON_0 (SPM_BASE + 0x650) 350 #define SPM_RSV_CON_1 (SPM_BASE + 0x654) 351 #define SPM_RSV_STA_0 (SPM_BASE + 0x658) 352 #define SPM_RSV_STA_1 (SPM_BASE + 0x65C) 353 #define SPM_SPARE_CON (SPM_BASE + 0x660) 354 #define SPM_SPARE_CON_SET (SPM_BASE + 0x664) 355 #define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) 356 #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) 357 #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) 358 #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) 359 #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) 360 #define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) 361 #define SC_MM_CK_SEL_CON (SPM_BASE + 0x680) 362 #define SPARE_ACK_MASK (SPM_BASE + 0x684) 363 #define SPM_CROSS_WAKE_M04_REQ (SPM_BASE + 0x688) 364 #define SPM_DV_CON_0 (SPM_BASE + 0x68C) 365 #define SPM_DV_CON_1 (SPM_BASE + 0x690) 366 #define SPM_DV_STA (SPM_BASE + 0x694) 367 #define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698) 368 #define SPM_SEMA_M0 (SPM_BASE + 0x69C) 369 #define SPM_SEMA_M1 (SPM_BASE + 0x6A0) 370 #define SPM_SEMA_M2 (SPM_BASE + 0x6A4) 371 #define SPM_SEMA_M3 (SPM_BASE + 0x6A8) 372 #define SPM_SEMA_M4 (SPM_BASE + 0x6AC) 373 #define SPM_SEMA_M5 (SPM_BASE + 0x6B0) 374 #define SPM_SEMA_M6 (SPM_BASE + 0x6B4) 375 #define SPM_SEMA_M7 (SPM_BASE + 0x6B8) 376 #define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) 377 #define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) 378 #define SPM_ADSP_IRQ (SPM_BASE + 0x6C4) 379 #define SPM_MD32_IRQ (SPM_BASE + 0x6C8) 380 #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) 381 #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) 382 #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) 383 #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) 384 #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) 385 #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) 386 #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) 387 #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) 388 #define UFS_PSRI_SW (SPM_BASE + 0x6EC) 389 #define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0) 390 #define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4) 391 #define SPM_AP_SEMA (SPM_BASE + 0x6F8) 392 #define SPM_SPM_SEMA (SPM_BASE + 0x6FC) 393 #define SPM_DVFS_CON (SPM_BASE + 0x700) 394 #define SPM_DVFS_CON_STA (SPM_BASE + 0x704) 395 #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708) 396 #define SPM_DVFS_CMD0 (SPM_BASE + 0x710) 397 #define SPM_DVFS_CMD1 (SPM_BASE + 0x714) 398 #define SPM_DVFS_CMD2 (SPM_BASE + 0x718) 399 #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) 400 #define SPM_DVFS_CMD4 (SPM_BASE + 0x720) 401 #define SPM_DVFS_CMD5 (SPM_BASE + 0x724) 402 #define SPM_DVFS_CMD6 (SPM_BASE + 0x728) 403 #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) 404 #define SPM_DVFS_CMD8 (SPM_BASE + 0x730) 405 #define SPM_DVFS_CMD9 (SPM_BASE + 0x734) 406 #define SPM_DVFS_CMD10 (SPM_BASE + 0x738) 407 #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) 408 #define SPM_DVFS_CMD12 (SPM_BASE + 0x740) 409 #define SPM_DVFS_CMD13 (SPM_BASE + 0x744) 410 #define SPM_DVFS_CMD14 (SPM_BASE + 0x748) 411 #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) 412 #define SPM_DVFS_CMD16 (SPM_BASE + 0x750) 413 #define SPM_DVFS_CMD17 (SPM_BASE + 0x754) 414 #define SPM_DVFS_CMD18 (SPM_BASE + 0x758) 415 #define SPM_DVFS_CMD19 (SPM_BASE + 0x75C) 416 #define SPM_DVFS_CMD20 (SPM_BASE + 0x760) 417 #define SPM_DVFS_CMD21 (SPM_BASE + 0x764) 418 #define SPM_DVFS_CMD22 (SPM_BASE + 0x768) 419 #define SPM_DVFS_CMD23 (SPM_BASE + 0x76C) 420 #define SYS_TIMER_VALUE_L (SPM_BASE + 0x770) 421 #define SYS_TIMER_VALUE_H (SPM_BASE + 0x774) 422 #define SYS_TIMER_START_L (SPM_BASE + 0x778) 423 #define SYS_TIMER_START_H (SPM_BASE + 0x77C) 424 #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780) 425 #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784) 426 #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788) 427 #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C) 428 #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790) 429 #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794) 430 #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798) 431 #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C) 432 #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0) 433 #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4) 434 #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8) 435 #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC) 436 #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0) 437 #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4) 438 #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8) 439 #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC) 440 #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0) 441 #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4) 442 #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8) 443 #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC) 444 #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0) 445 #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4) 446 #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8) 447 #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC) 448 #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0) 449 #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4) 450 #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8) 451 #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC) 452 #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0) 453 #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4) 454 #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8) 455 #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC) 456 #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) 457 #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) 458 #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) 459 #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) 460 #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) 461 #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) 462 #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) 463 #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) 464 #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) 465 #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) 466 #define PCM_WDT_LATCH_10 (SPM_BASE + 0x828) 467 #define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C) 468 #define PCM_WDT_LATCH_12 (SPM_BASE + 0x830) 469 #define PCM_WDT_LATCH_13 (SPM_BASE + 0x834) 470 #define PCM_WDT_LATCH_14 (SPM_BASE + 0x838) 471 #define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C) 472 #define PCM_WDT_LATCH_16 (SPM_BASE + 0x840) 473 #define PCM_WDT_LATCH_17 (SPM_BASE + 0x844) 474 #define PCM_WDT_LATCH_18 (SPM_BASE + 0x848) 475 #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C) 476 #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850) 477 #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854) 478 #define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870) 479 #define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874) 480 #define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878) 481 #define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0) 482 #define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4) 483 #define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8) 484 #define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC) 485 #define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0) 486 #define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4) 487 #define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8) 488 #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4) 489 #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900) 490 #define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904) 491 #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908) 492 #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C) 493 #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910) 494 #define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914) 495 #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920) 496 #define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924) 497 #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928) 498 #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C) 499 #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930) 500 #define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934) 501 #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940) 502 #define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944) 503 #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948) 504 #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C) 505 #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950) 506 #define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954) 507 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) 508 #define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964) 509 #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968) 510 #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C) 511 #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970) 512 #define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974) 513 #define SPM_COUNTER_0 (SPM_BASE + 0x978) 514 #define SPM_COUNTER_1 (SPM_BASE + 0x97C) 515 #define SPM_COUNTER_2 (SPM_BASE + 0x980) 516 #define SYS_TIMER_CON (SPM_BASE + 0x98C) 517 #define RC_FSM_STA_0 (SPM_BASE + 0xE00) 518 #define RC_CMD_STA_0 (SPM_BASE + 0xE04) 519 #define RC_CMD_STA_1 (SPM_BASE + 0xE08) 520 #define RC_SPI_STA_0 (SPM_BASE + 0xE0C) 521 #define RC_PI_PO_STA_0 (SPM_BASE + 0xE10) 522 #define RC_M00_REQ_STA_0 (SPM_BASE + 0xE14) 523 #define RC_M01_REQ_STA_0 (SPM_BASE + 0xE1C) 524 #define RC_M02_REQ_STA_0 (SPM_BASE + 0xE20) 525 #define RC_M03_REQ_STA_0 (SPM_BASE + 0xE24) 526 #define RC_M04_REQ_STA_0 (SPM_BASE + 0xE28) 527 #define RC_M05_REQ_STA_0 (SPM_BASE + 0xE2C) 528 #define RC_M06_REQ_STA_0 (SPM_BASE + 0xE30) 529 #define RC_M07_REQ_STA_0 (SPM_BASE + 0xE34) 530 #define RC_M08_REQ_STA_0 (SPM_BASE + 0xE38) 531 #define RC_M09_REQ_STA_0 (SPM_BASE + 0xE3C) 532 #define RC_M10_REQ_STA_0 (SPM_BASE + 0xE40) 533 #define RC_M11_REQ_STA_0 (SPM_BASE + 0xE44) 534 #define RC_M12_REQ_STA_0 (SPM_BASE + 0xE48) 535 #define RC_DEBUG_STA_0 (SPM_BASE + 0xE4C) 536 #define RC_DEBUG_TRACE_0_LSB (SPM_BASE + 0xE50) 537 #define RC_DEBUG_TRACE_0_MSB (SPM_BASE + 0xE54) 538 #define RC_DEBUG_TRACE_1_LSB (SPM_BASE + 0xE5C) 539 #define RC_DEBUG_TRACE_1_MSB (SPM_BASE + 0xE60) 540 #define RC_DEBUG_TRACE_2_LSB (SPM_BASE + 0xE64) 541 #define RC_DEBUG_TRACE_2_MSB (SPM_BASE + 0xE6C) 542 #define RC_DEBUG_TRACE_3_LSB (SPM_BASE + 0xE70) 543 #define RC_DEBUG_TRACE_3_MSB (SPM_BASE + 0xE74) 544 #define RC_DEBUG_TRACE_4_LSB (SPM_BASE + 0xE78) 545 #define RC_DEBUG_TRACE_4_MSB (SPM_BASE + 0xE7C) 546 #define RC_DEBUG_TRACE_5_LSB (SPM_BASE + 0xE80) 547 #define RC_DEBUG_TRACE_5_MSB (SPM_BASE + 0xE84) 548 #define RC_DEBUG_TRACE_6_LSB (SPM_BASE + 0xE88) 549 #define RC_DEBUG_TRACE_6_MSB (SPM_BASE + 0xE8C) 550 #define RC_DEBUG_TRACE_7_LSB (SPM_BASE + 0xE90) 551 #define RC_DEBUG_TRACE_7_MSB (SPM_BASE + 0xE94) 552 #define RC_SYS_TIMER_LATCH_0_LSB (SPM_BASE + 0xE98) 553 #define RC_SYS_TIMER_LATCH_0_MSB (SPM_BASE + 0xE9C) 554 #define RC_SYS_TIMER_LATCH_1_LSB (SPM_BASE + 0xEA0) 555 #define RC_SYS_TIMER_LATCH_1_MSB (SPM_BASE + 0xEA4) 556 #define RC_SYS_TIMER_LATCH_2_LSB (SPM_BASE + 0xEA8) 557 #define RC_SYS_TIMER_LATCH_2_MSB (SPM_BASE + 0xEAC) 558 #define RC_SYS_TIMER_LATCH_3_LSB (SPM_BASE + 0xEB0) 559 #define RC_SYS_TIMER_LATCH_3_MSB (SPM_BASE + 0xEB4) 560 #define RC_SYS_TIMER_LATCH_4_LSB (SPM_BASE + 0xEB8) 561 #define RC_SYS_TIMER_LATCH_4_MSB (SPM_BASE + 0xEBC) 562 #define RC_SYS_TIMER_LATCH_5_LSB (SPM_BASE + 0xEC0) 563 #define RC_SYS_TIMER_LATCH_5_MSB (SPM_BASE + 0xEC4) 564 #define RC_SYS_TIMER_LATCH_6_LSB (SPM_BASE + 0xEC8) 565 #define RC_SYS_TIMER_LATCH_6_MSB (SPM_BASE + 0xECC) 566 #define RC_SYS_TIMER_LATCH_7_LSB (SPM_BASE + 0xED0) 567 #define RC_SYS_TIMER_LATCH_7_MSB (SPM_BASE + 0xED4) 568 #define PCM_WDT_LATCH_19 (SPM_BASE + 0xED8) 569 #define PCM_WDT_LATCH_20 (SPM_BASE + 0xEDC) 570 #define PCM_WDT_LATCH_21 (SPM_BASE + 0xEE0) 571 #define PCM_WDT_LATCH_22 (SPM_BASE + 0xEE4) 572 #define PCM_WDT_LATCH_23 (SPM_BASE + 0xEE8) 573 #define PCM_WDT_LATCH_24 (SPM_BASE + 0xEEC) 574 #define PMSR_LAST_DAT (SPM_BASE + 0xF00) 575 #define PMSR_LAST_CNT (SPM_BASE + 0xF04) 576 #define PMSR_LAST_ACK (SPM_BASE + 0xF08) 577 #define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10) 578 #define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14) 579 #define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18) 580 #define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C) 581 #define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20) 582 #define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24) 583 #define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28) 584 #define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C) 585 #define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30) 586 #define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34) 587 #define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C) 588 #define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40) 589 #define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8) 590 #define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC) 591 #define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0) 592 #define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4) 593 #define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8) 594 #define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC) 595 #define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0) 596 #define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4) 597 #define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8) 598 #define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC) 599 #define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0) 600 #define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4) 601 #define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8) 602 #define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC) 603 #define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0) 604 #define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4) 605 606 /* POWERON_CONFIG_EN (0x10006000+0x000) */ 607 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ 608 #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 609 /* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ 610 #define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ 611 /* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ 612 #define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ 613 /* SPM_CLK_CON (0x10006000+0x00C) */ 614 #define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */ 615 #define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */ 616 #define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ 617 #define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ 618 #define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ 619 #define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */ 620 #define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */ 621 #define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ 622 #define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ 623 #define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */ 624 #define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */ 625 #define SCP_DCM_EN_LSB (1U << 15) /* 1b */ 626 #define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */ 627 #define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */ 628 /* SPM_CLK_SETTLE (0x10006000+0x010) */ 629 #define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ 630 /* SPM_AP_STANDBY_CON (0x10006000+0x014) */ 631 #define REG_WFI_OP_LSB (1U << 0) /* 1b */ 632 #define REG_WFI_TYPE_LSB (1U << 1) /* 1b */ 633 #define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ 634 #define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */ 635 #define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ 636 #define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ 637 #define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ 638 #define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ 639 /* PCM_CON0 (0x10006000+0x018) */ 640 #define PCM_CK_EN_LSB (1U << 2) /* 1b */ 641 #define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ 642 #define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */ 643 #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ 644 #define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */ 645 /* PCM_CON1 (0x10006000+0x01C) */ 646 #define RG_IM_SLAVE_LSB (1U << 0) /* 1b */ 647 #define RG_IM_SLEEP_LSB (1U << 1) /* 1b */ 648 #define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */ 649 #define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ 650 #define RG_IM_PDN_LSB (1U << 4) /* 1b */ 651 #define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ 652 #define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ 653 #define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */ 654 #define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */ 655 #define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ 656 #define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ 657 #define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ 658 #define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ 659 #define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ 660 #define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ 661 #define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */ 662 #define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */ 663 /* SPM_POWER_ON_VAL2 (0x10006000+0x020) */ 664 #define POWER_ON_VAL2_LSB (1U << 0) /* 32b */ 665 /* SPM_POWER_ON_VAL3 (0x10006000+0x024) */ 666 #define POWER_ON_VAL3_LSB (1U << 0) /* 32b */ 667 /* PCM_REG_DATA_INI (0x10006000+0x028) */ 668 #define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ 669 /* PCM_PWR_IO_EN (0x10006000+0x02C) */ 670 #define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ 671 #define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */ 672 /* PCM_TIMER_VAL (0x10006000+0x030) */ 673 #define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ 674 /* PCM_WDT_VAL (0x10006000+0x034) */ 675 #define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */ 676 /* SPM_SRC6_MASK (0x10006000+0x038) */ 677 #define REG_DPMAIF_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ 678 #define REG_DPMAIF_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ 679 #define REG_DPMAIF_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ 680 #define REG_DPMAIF_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ 681 #define REG_DPMAIF_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ 682 /* SPM_SW_RST_CON (0x10006000+0x040) */ 683 #define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */ 684 #define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */ 685 /* SPM_SW_RST_CON_SET (0x10006000+0x044) */ 686 #define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */ 687 #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */ 688 /* SPM_SW_RST_CON_CLR (0x10006000+0x048) */ 689 #define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */ 690 #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */ 691 /* VS1_PSR_MASK_B (0x10006000+0x04C) */ 692 #define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ 693 #define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ 694 /* VS2_PSR_MASK_B (0x10006000+0x050) */ 695 #define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ 696 #define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ 697 #define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */ 698 /* MD32_CLK_CON (0x10006000+0x084) */ 699 #define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */ 700 #define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */ 701 /* SPM_SRAM_RSV_CON (0x10006000+0x088) */ 702 #define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ 703 /* SPM_SWINT (0x10006000+0x08C) */ 704 #define SPM_SWINT_LSB (1U << 0) /* 32b */ 705 /* SPM_SWINT_SET (0x10006000+0x090) */ 706 #define SPM_SWINT_SET_LSB (1U << 0) /* 32b */ 707 /* SPM_SWINT_CLR (0x10006000+0x094) */ 708 #define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */ 709 /* SPM_SCP_MAILBOX (0x10006000+0x098) */ 710 #define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ 711 /* SCP_SPM_MAILBOX (0x10006000+0x09C) */ 712 #define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ 713 /* SPM_TWAM_CON (0x10006000+0x0A0) */ 714 #define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */ 715 #define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */ 716 #define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */ 717 #define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */ 718 #define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */ 719 #define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */ 720 #define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */ 721 #define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */ 722 /* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ 723 #define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ 724 /* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ 725 #define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */ 726 #define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */ 727 #define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */ 728 #define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */ 729 /* SPM_SCP_IRQ (0x10006000+0x0AC) */ 730 #define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */ 731 #define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ 732 /* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ 733 #define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */ 734 /* SPM_IRQ_MASK (0x10006000+0x0B4) */ 735 #define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */ 736 /* SPM_SRC_REQ (0x10006000+0x0B8) */ 737 #define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ 738 #define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */ 739 #define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ 740 #define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ 741 #define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */ 742 #define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */ 743 #define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */ 744 #define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */ 745 #define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */ 746 #define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */ 747 /* SPM_SRC_MASK (0x10006000+0x0BC) */ 748 #define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */ 749 #define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */ 750 #define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */ 751 #define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */ 752 #define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */ 753 #define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */ 754 #define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */ 755 #define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */ 756 #define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */ 757 #define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */ 758 #define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */ 759 #define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */ 760 #define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ 761 #define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */ 762 #define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */ 763 #define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ 764 #define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */ 765 #define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */ 766 #define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */ 767 #define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */ 768 #define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */ 769 #define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */ 770 #define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ 771 #define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 772 #define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 773 #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 774 #define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ 775 #define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ 776 #define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ 777 #define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 778 #define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 779 #define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 780 /* SPM_SRC2_MASK (0x10006000+0x0C0) */ 781 #define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ 782 #define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ 783 #define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ 784 #define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ 785 #define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ 786 #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ 787 #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ 788 #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ 789 #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ 790 #define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */ 791 #define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */ 792 #define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ 793 #define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */ 794 #define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */ 795 #define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */ 796 #define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ 797 #define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ 798 #define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */ 799 #define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */ 800 #define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ 801 #define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ 802 #define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ 803 #define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ 804 #define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 805 #define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 806 #define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 807 #define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ 808 #define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ 809 #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */ 810 #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 811 #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 812 #define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 813 /* SPM_SRC3_MASK (0x10006000+0x0C4) */ 814 #define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */ 815 #define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */ 816 #define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */ 817 #define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */ 818 #define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */ 819 #define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */ 820 #define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */ 821 #define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */ 822 #define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */ 823 #define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */ 824 #define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */ 825 #define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */ 826 #define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */ 827 #define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */ 828 #define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ 829 #define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */ 830 #define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */ 831 #define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ 832 #define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */ 833 #define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */ 834 #define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ 835 #define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ 836 #define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */ 837 #define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ 838 #define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ 839 #define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ 840 #define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 841 #define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 842 #define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 843 /* SPM_SRC4_MASK (0x10006000+0x0C8) */ 844 #define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */ 845 #define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */ 846 #define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */ 847 #define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */ 848 #define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */ 849 #define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */ 850 #define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */ 851 #define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */ 852 #define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ 853 #define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */ 854 #define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */ 855 #define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */ 856 #define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */ 857 /* SPM_SRC5_MASK (0x10006000+0x0CC) */ 858 #define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */ 859 #define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */ 860 #define REG_MSDC2_SRCCLKENA_MASK_B_LSB (1U << 18) /* 1b */ 861 #define REG_MSDC2_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ 862 #define REG_MSDC2_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ 863 #define REG_MSDC2_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ 864 #define REG_MSDC2_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ 865 #define REG_PCIE_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 866 #define REG_PCIE_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 867 #define REG_PCIE_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 868 #define REG_PCIE_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ 869 #define REG_PCIE_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ 870 /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ 871 #define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 872 /* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */ 873 #define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 874 /* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */ 875 #define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ 876 /* SCP_CLK_CON (0x10006000+0x0DC) */ 877 #define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ 878 #define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */ 879 #define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */ 880 #define SCP_SLP_REQ_LSB (1U << 3) /* 1b */ 881 #define SCP_SLP_ACK_LSB (1U << 4) /* 1b */ 882 /* PCM_DEBUG_CON (0x10006000+0x0E0) */ 883 #define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ 884 /* AHB_BUS_CON (0x10006000+0x0E4) */ 885 #define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ 886 #define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ 887 /* DDR_EN_DBC_CON0 (0x10006000+0x0E8) */ 888 #define REG_ALL_DDR_EN_DBC_LEN_LSB (1U << 0) /* 10b */ 889 #define REG_MD_DDR_EN_0_DBC_LEN_LSB (1U << 10) /* 10b */ 890 #define REG_HW_S1_DBC_LEN_LSB (1U << 20) /* 10b */ 891 /* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */ 892 #define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */ 893 #define REG_MD_DDR_EN_0_DBC_EN_LSB (1U << 1) /* 1b */ 894 #define REG_HW_S1_DBC_EN_LSB (1U << 2) /* 1b */ 895 /* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */ 896 #define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */ 897 #define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */ 898 #define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */ 899 #define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */ 900 #define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */ 901 #define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */ 902 #define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */ 903 #define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */ 904 #define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */ 905 #define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */ 906 #define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ 907 #define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ 908 #define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ 909 #define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ 910 #define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ 911 #define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ 912 #define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ 913 #define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ 914 #define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ 915 #define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ 916 #define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ 917 #define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ 918 #define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ 919 #define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ 920 #define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ 921 #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */ 922 #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */ 923 #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */ 924 #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */ 925 #define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */ 926 #define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ 927 #define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */ 928 /* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */ 929 #define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ 930 #define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ 931 #define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ 932 #define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ 933 #define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */ 934 #define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */ 935 #define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */ 936 #define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */ 937 #define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */ 938 #define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */ 939 #define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ 940 #define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ 941 #define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ 942 #define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ 943 #define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ 944 #define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ 945 #define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ 946 #define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ 947 #define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ 948 #define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ 949 #define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ 950 #define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ 951 #define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ 952 #define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ 953 #define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ 954 #define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ 955 #define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */ 956 #define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */ 957 #define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */ 958 #define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */ 959 #define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ 960 /* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */ 961 #define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ 962 #define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */ 963 #define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */ 964 #define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */ 965 /* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */ 966 #define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ 967 #define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */ 968 #define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */ 969 #define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */ 970 #define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */ 971 #define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */ 972 #define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB (1U << 13) /* 1b */ 973 #define REG_MSDC2_INFRA_ACK_MASK_LSB (1U << 14) /* 1b */ 974 #define REG_MSDC2_APSRC_ACK_MASK_LSB (1U << 15) /* 1b */ 975 #define REG_MSDC2_VRF18_ACK_MASK_LSB (1U << 16) /* 1b */ 976 #define REG_MSDC2_DDR_EN_ACK_MASK_LSB (1U << 17) /* 1b */ 977 #define REG_PCIE_SRCCLKENA_ACK_MASK_LSB (1U << 18) /* 1b */ 978 #define REG_PCIE_INFRA_ACK_MASK_LSB (1U << 19) /* 1b */ 979 #define REG_PCIE_APSRC_ACK_MASK_LSB (1U << 20) /* 1b */ 980 #define REG_PCIE_VRF18_ACK_MASK_LSB (1U << 21) /* 1b */ 981 #define REG_PCIE_DDR_EN_ACK_MASK_LSB (1U << 22) /* 1b */ 982 #define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB (1U << 23) /* 1b */ 983 #define REG_DPMAIF_INFRA_ACK_MASK_LSB (1U << 24) /* 1b */ 984 #define REG_DPMAIF_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ 985 #define REG_DPMAIF_VRF18_ACK_MASK_LSB (1U << 26) /* 1b */ 986 #define REG_DPMAIF_DDR_EN_ACK_MASK_LSB (1U << 27) /* 1b */ 987 /* PCM_REG0_DATA (0x10006000+0x100) */ 988 #define PCM_REG0_RF_LSB (1U << 0) /* 32b */ 989 /* PCM_REG2_DATA (0x10006000+0x104) */ 990 #define PCM_REG2_RF_LSB (1U << 0) /* 32b */ 991 /* PCM_REG6_DATA (0x10006000+0x108) */ 992 #define PCM_REG6_RF_LSB (1U << 0) /* 32b */ 993 /* PCM_REG7_DATA (0x10006000+0x10C) */ 994 #define PCM_REG7_RF_LSB (1U << 0) /* 32b */ 995 /* PCM_REG13_DATA (0x10006000+0x110) */ 996 #define PCM_REG13_RF_LSB (1U << 0) /* 32b */ 997 /* SRC_REQ_STA_0 (0x10006000+0x114) */ 998 #define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */ 999 #define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */ 1000 #define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */ 1001 #define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */ 1002 #define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */ 1003 #define MD_DDR_EN_0_LSB (1U << 5) /* 1b */ 1004 #define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */ 1005 #define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */ 1006 #define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */ 1007 #define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */ 1008 #define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */ 1009 #define MD_DDR_EN_1_LSB (1U << 11) /* 1b */ 1010 #define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */ 1011 #define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */ 1012 #define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */ 1013 #define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */ 1014 #define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */ 1015 #define CONN_DDR_EN_LSB (1U << 17) /* 1b */ 1016 #define SRCCLKENI_LSB (1U << 18) /* 3b */ 1017 #define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */ 1018 #define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */ 1019 #define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */ 1020 #define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */ 1021 #define MD32_DDR_EN_LSB (1U << 25) /* 1b */ 1022 #define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */ 1023 #define DISP0_DDR_EN_LSB (1U << 27) /* 1b */ 1024 #define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */ 1025 #define DISP1_DDR_EN_LSB (1U << 29) /* 1b */ 1026 #define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */ 1027 /* SRC_REQ_STA_1 (0x10006000+0x118) */ 1028 #define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */ 1029 #define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */ 1030 #define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */ 1031 #define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */ 1032 #define SCP_DDR_EN_LSB (1U << 4) /* 1b */ 1033 #define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */ 1034 #define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */ 1035 #define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */ 1036 #define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */ 1037 #define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */ 1038 #define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */ 1039 #define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */ 1040 #define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */ 1041 #define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */ 1042 #define UFS_DDR_EN_LSB (1U << 14) /* 1b */ 1043 #define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */ 1044 #define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */ 1045 #define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */ 1046 #define GCE_DDR_EN_LSB (1U << 18) /* 1b */ 1047 #define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */ 1048 #define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */ 1049 #define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */ 1050 #define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */ 1051 #define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */ 1052 #define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */ 1053 #define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */ 1054 #define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */ 1055 #define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */ 1056 #define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */ 1057 #define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */ 1058 #define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */ 1059 /* SRC_REQ_STA_2 (0x10006000+0x11C) */ 1060 #define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */ 1061 #define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */ 1062 #define SW2SPM_INT_LSB (1U << 11) /* 4b */ 1063 #define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */ 1064 #define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */ 1065 #define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */ 1066 #define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */ 1067 #define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */ 1068 #define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */ 1069 #define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */ 1070 #define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */ 1071 #define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */ 1072 #define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */ 1073 #define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */ 1074 #define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */ 1075 #define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */ 1076 /* PCM_TIMER_OUT (0x10006000+0x120) */ 1077 #define PCM_TIMER_LSB (1U << 0) /* 32b */ 1078 /* PCM_WDT_OUT (0x10006000+0x124) */ 1079 #define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */ 1080 /* SPM_IRQ_STA (0x10006000+0x128) */ 1081 #define TWAM_IRQ_LSB (1U << 2) /* 1b */ 1082 #define PCM_IRQ_LSB (1U << 3) /* 1b */ 1083 /* SRC_REQ_STA_4 (0x10006000+0x12C) */ 1084 #define APU_SRCCLKENA_LSB (1U << 0) /* 1b */ 1085 #define APU_INFRA_REQ_LSB (1U << 1) /* 1b */ 1086 #define APU_APSRC_REQ_LSB (1U << 2) /* 1b */ 1087 #define APU_VRF18_REQ_LSB (1U << 3) /* 1b */ 1088 #define APU_DDR_EN_LSB (1U << 4) /* 1b */ 1089 #define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */ 1090 #define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */ 1091 #define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */ 1092 #define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */ 1093 #define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */ 1094 #define MSDC2_SRCCLKENA_LSB (1U << 10) /* 1b */ 1095 #define MSDC2_INFRA_REQ_LSB (1U << 11) /* 1b */ 1096 #define MSDC2_APSRC_REQ_LSB (1U << 12) /* 1b */ 1097 #define MSDC2_VRF18_REQ_LSB (1U << 13) /* 1b */ 1098 #define MSDC2_DDR_EN_LSB (1U << 14) /* 1b */ 1099 #define PCIE_SRCCLKENA_LSB (1U << 15) /* 1b */ 1100 #define PCIE_INFRA_REQ_LSB (1U << 16) /* 1b */ 1101 #define PCIE_APSRC_REQ_LSB (1U << 17) /* 1b */ 1102 #define PCIE_VRF18_REQ_LSB (1U << 18) /* 1b */ 1103 #define PCIE_DDR_EN_LSB (1U << 19) /* 1b */ 1104 #define DPMAIF_SRCCLKENA_LSB (1U << 20) /* 1b */ 1105 #define DPMAIF_INFRA_REQ_LSB (1U << 21) /* 1b */ 1106 #define DPMAIF_APSRC_REQ_LSB (1U << 22) /* 1b */ 1107 #define DPMAIF_VRF18_REQ_LSB (1U << 23) /* 1b */ 1108 #define DPMAIF_DDR_EN_LSB (1U << 24) /* 1b */ 1109 /* MD32PCM_WAKEUP_STA (0x10006000+0x130) */ 1110 #define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */ 1111 /* MD32PCM_EVENT_STA (0x10006000+0x134) */ 1112 #define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */ 1113 /* SPM_WAKEUP_STA (0x10006000+0x138) */ 1114 #define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */ 1115 #define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */ 1116 /* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */ 1117 #define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */ 1118 /* SPM_WAKEUP_MISC (0x10006000+0x140) */ 1119 #define GIC_WAKEUP_LSB (1U << 0) /* 10b */ 1120 #define DVFSRC_IRQ_LSB (1U << 16) /* 1b */ 1121 #define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */ 1122 #define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */ 1123 #define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */ 1124 #define TWAM_IRQ_B_LSB (1U << 21) /* 1b */ 1125 #define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */ 1126 #define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */ 1127 #define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */ 1128 #define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */ 1129 #define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */ 1130 #define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */ 1131 #define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */ 1132 #define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */ 1133 #define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */ 1134 #define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */ 1135 /* MM_DVFS_HALT (0x10006000+0x144) */ 1136 #define MM_DVFS_HALT_LSB (1U << 0) /* 5b */ 1137 /* BUS_PROTECT_RDY (0x10006000+0x150) */ 1138 #define PROTECT_READY_LSB (1U << 0) /* 32b */ 1139 /* BUS_PROTECT1_RDY (0x10006000+0x154) */ 1140 #define PROTECT1_READY_LSB (1U << 0) /* 32b */ 1141 /* BUS_PROTECT2_RDY (0x10006000+0x158) */ 1142 #define PROTECT2_READY_LSB (1U << 0) /* 32b */ 1143 /* BUS_PROTECT3_RDY (0x10006000+0x15C) */ 1144 #define PROTECT3_READY_LSB (1U << 0) /* 32b */ 1145 /* SUBSYS_IDLE_STA (0x10006000+0x160) */ 1146 #define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */ 1147 /* PCM_STA (0x10006000+0x164) */ 1148 #define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */ 1149 #define EXT_SRC_STA_LSB (1U << 4) /* 3b */ 1150 /* SRC_REQ_STA_3 (0x10006000+0x168) */ 1151 #define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */ 1152 #define F26M_STATE_LSB (1U << 16) /* 1b */ 1153 #define INFRA_STATE_LSB (1U << 17) /* 1b */ 1154 #define APSRC_STATE_LSB (1U << 18) /* 1b */ 1155 #define VRF18_STATE_LSB (1U << 19) /* 1b */ 1156 #define DDR_EN_STATE_LSB (1U << 20) /* 1b */ 1157 #define DVFS_STATE_LSB (1U << 21) /* 1b */ 1158 #define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */ 1159 #define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */ 1160 #define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */ 1161 #define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */ 1162 /* PWR_STATUS (0x10006000+0x16C) */ 1163 #define PWR_STATUS_LSB (1U << 0) /* 32b */ 1164 /* PWR_STATUS_2ND (0x10006000+0x170) */ 1165 #define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ 1166 /* CPU_PWR_STATUS (0x10006000+0x174) */ 1167 #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */ 1168 #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */ 1169 #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */ 1170 #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */ 1171 #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */ 1172 #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */ 1173 #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */ 1174 #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */ 1175 #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */ 1176 #define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */ 1177 /* OTHER_PWR_STATUS (0x10006000+0x178) */ 1178 #define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */ 1179 /* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */ 1180 #define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1181 #define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1182 /* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */ 1183 #define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1184 #define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1185 /* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */ 1186 #define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1187 #define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1188 /* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */ 1189 #define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1190 #define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1191 /* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */ 1192 #define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1193 #define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1194 /* MD32PCM_STA (0x10006000+0x190) */ 1195 #define MD32PCM_HALT_LSB (1U << 0) /* 1b */ 1196 #define MD32PCM_GATED_LSB (1U << 1) /* 1b */ 1197 /* MD32PCM_PC (0x10006000+0x194) */ 1198 #define MON_PC_LSB (1U << 0) /* 32b */ 1199 /* DVFSRC_EVENT_STA (0x10006000+0x1A4) */ 1200 #define DVFSRC_EVENT_LSB (1U << 0) /* 32b */ 1201 /* BUS_PROTECT4_RDY (0x10006000+0x1A8) */ 1202 #define PROTECT4_READY_LSB (1U << 0) /* 32b */ 1203 /* BUS_PROTECT5_RDY (0x10006000+0x1AC) */ 1204 #define PROTECT5_READY_LSB (1U << 0) /* 32b */ 1205 /* BUS_PROTECT6_RDY (0x10006000+0x1B0) */ 1206 #define PROTECT6_READY_LSB (1U << 0) /* 32b */ 1207 /* BUS_PROTECT7_RDY (0x10006000+0x1B4) */ 1208 #define PROTECT7_READY_LSB (1U << 0) /* 32b */ 1209 /* BUS_PROTECT8_RDY (0x10006000+0x1B8) */ 1210 #define PROTECT8_READY_LSB (1U << 0) /* 32b */ 1211 /* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */ 1212 #define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */ 1213 /* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */ 1214 #define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */ 1215 /* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */ 1216 #define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */ 1217 /* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */ 1218 #define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */ 1219 /* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */ 1220 #define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */ 1221 /* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */ 1222 #define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */ 1223 /* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */ 1224 #define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */ 1225 /* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */ 1226 #define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */ 1227 /* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */ 1228 #define TWAM_TIMER_LSB (1U << 0) /* 32b */ 1229 /* SPM_CG_CHECK_STA (0x10006000+0x1F4) */ 1230 #define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */ 1231 #define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */ 1232 #define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */ 1233 /* SPM_DVFS_STA (0x10006000+0x1F8) */ 1234 #define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1235 /* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */ 1236 #define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */ 1237 #define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */ 1238 #define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */ 1239 /* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */ 1240 #define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1241 #define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */ 1242 #define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1243 #define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */ 1244 #define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */ 1245 #define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ 1246 #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */ 1247 /* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */ 1248 #define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */ 1249 #define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */ 1250 #define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */ 1251 #define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */ 1252 #define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */ 1253 #define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ 1254 #define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */ 1255 #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */ 1256 /* SPM_CPU0_PWR_CON (0x10006000+0x208) */ 1257 #define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */ 1258 #define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */ 1259 #define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */ 1260 #define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */ 1261 #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */ 1262 /* SPM_CPU1_PWR_CON (0x10006000+0x20C) */ 1263 #define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */ 1264 #define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */ 1265 #define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */ 1266 #define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */ 1267 #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */ 1268 /* SPM_CPU2_PWR_CON (0x10006000+0x210) */ 1269 #define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */ 1270 #define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */ 1271 #define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */ 1272 #define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */ 1273 #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */ 1274 /* SPM_CPU3_PWR_CON (0x10006000+0x214) */ 1275 #define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */ 1276 #define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */ 1277 #define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */ 1278 #define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */ 1279 #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */ 1280 /* SPM_CPU4_PWR_CON (0x10006000+0x218) */ 1281 #define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */ 1282 #define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */ 1283 #define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */ 1284 #define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */ 1285 #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */ 1286 /* SPM_CPU5_PWR_CON (0x10006000+0x21C) */ 1287 #define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */ 1288 #define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */ 1289 #define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */ 1290 #define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */ 1291 #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */ 1292 /* SPM_CPU6_PWR_CON (0x10006000+0x220) */ 1293 #define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */ 1294 #define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */ 1295 #define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */ 1296 #define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */ 1297 #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */ 1298 /* SPM_CPU7_PWR_CON (0x10006000+0x224) */ 1299 #define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */ 1300 #define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */ 1301 #define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */ 1302 #define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */ 1303 #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */ 1304 /* ARMPLL_CLK_CON (0x10006000+0x22C) */ 1305 #define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */ 1306 #define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */ 1307 #define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */ 1308 #define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */ 1309 #define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */ 1310 #define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */ 1311 #define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */ 1312 #define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */ 1313 #define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */ 1314 #define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */ 1315 #define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */ 1316 #define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */ 1317 #define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */ 1318 #define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */ 1319 #define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */ 1320 #define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */ 1321 #define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */ 1322 #define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */ 1323 #define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */ 1324 #define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */ 1325 /* MCUSYS_IDLE_STA (0x10006000+0x230) */ 1326 #define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */ 1327 #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */ 1328 #define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */ 1329 #define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */ 1330 #define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */ 1331 #define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */ 1332 #define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */ 1333 #define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */ 1334 #define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */ 1335 #define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */ 1336 #define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */ 1337 #define WFI_AF_SEL_LSB (1U << 24) /* 8b */ 1338 /* GIC_WAKEUP_STA (0x10006000+0x234) */ 1339 #define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */ 1340 /* CPU_SPARE_CON (0x10006000+0x238) */ 1341 #define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ 1342 /* CPU_SPARE_CON_SET (0x10006000+0x23C) */ 1343 #define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 1344 /* CPU_SPARE_CON_CLR (0x10006000+0x240) */ 1345 #define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 1346 /* ARMPLL_CLK_SEL (0x10006000+0x244) */ 1347 #define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */ 1348 /* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */ 1349 #define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */ 1350 /* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */ 1351 #define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */ 1352 /* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */ 1353 #define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */ 1354 /* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */ 1355 #define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 1356 #define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ 1357 /* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */ 1358 #define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 1359 #define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ 1360 /* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */ 1361 #define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 1362 #define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ 1363 /* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */ 1364 #define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 1365 #define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ 1366 /* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */ 1367 #define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 1368 #define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ 1369 /* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */ 1370 #define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 1371 #define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ 1372 /* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */ 1373 #define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 1374 #define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ 1375 /* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */ 1376 #define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 1377 #define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ 1378 /* MP0_CPU0_WFI_EN (0x10006000+0x280) */ 1379 #define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ 1380 /* MP0_CPU1_WFI_EN (0x10006000+0x284) */ 1381 #define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ 1382 /* MP0_CPU2_WFI_EN (0x10006000+0x288) */ 1383 #define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ 1384 /* MP0_CPU3_WFI_EN (0x10006000+0x28C) */ 1385 #define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ 1386 /* MP0_CPU4_WFI_EN (0x10006000+0x290) */ 1387 #define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */ 1388 /* MP0_CPU5_WFI_EN (0x10006000+0x294) */ 1389 #define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */ 1390 /* MP0_CPU6_WFI_EN (0x10006000+0x298) */ 1391 #define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */ 1392 /* MP0_CPU7_WFI_EN (0x10006000+0x29C) */ 1393 #define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */ 1394 /* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */ 1395 #define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ 1396 /* ROOT_CORE_ADDR (0x10006000+0x2A4) */ 1397 #define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ 1398 /* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */ 1399 #define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ 1400 /* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */ 1401 #define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ 1402 /* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */ 1403 #define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ 1404 /* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */ 1405 #define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ 1406 /* SW2SPM_INT (0x10006000+0x2E0) */ 1407 #define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */ 1408 /* SW2SPM_INT_SET (0x10006000+0x2E4) */ 1409 #define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ 1410 /* SW2SPM_INT_CLR (0x10006000+0x2E8) */ 1411 #define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ 1412 /* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */ 1413 #define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 1414 /* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */ 1415 #define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 1416 /* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */ 1417 #define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 1418 /* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */ 1419 #define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 1420 /* SW2SPM_CFG (0x10006000+0x2FC) */ 1421 #define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ 1422 /* MD1_PWR_CON (0x10006000+0x300) */ 1423 #define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1424 #define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ 1425 #define MD1_PWR_ON_LSB (1U << 2) /* 1b */ 1426 #define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1427 #define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1428 #define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1429 #define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1430 /* CONN_PWR_CON (0x10006000+0x304) */ 1431 #define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1432 #define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ 1433 #define CONN_PWR_ON_LSB (1U << 2) /* 1b */ 1434 #define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1435 #define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1436 /* MFG0_PWR_CON (0x10006000+0x308) */ 1437 #define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */ 1438 #define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */ 1439 #define MFG0_PWR_ON_LSB (1U << 2) /* 1b */ 1440 #define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1441 #define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1442 #define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */ 1443 #define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1444 /* MFG1_PWR_CON (0x10006000+0x30C) */ 1445 #define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1446 #define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */ 1447 #define MFG1_PWR_ON_LSB (1U << 2) /* 1b */ 1448 #define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1449 #define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1450 #define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1451 #define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1452 /* MFG2_PWR_CON (0x10006000+0x310) */ 1453 #define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1454 #define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */ 1455 #define MFG2_PWR_ON_LSB (1U << 2) /* 1b */ 1456 #define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1457 #define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1458 #define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1459 #define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1460 /* MFG3_PWR_CON (0x10006000+0x314) */ 1461 #define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */ 1462 #define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */ 1463 #define MFG3_PWR_ON_LSB (1U << 2) /* 1b */ 1464 #define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1465 #define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1466 #define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */ 1467 #define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1468 /* MFG4_PWR_CON (0x10006000+0x318) */ 1469 #define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */ 1470 #define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */ 1471 #define MFG4_PWR_ON_LSB (1U << 2) /* 1b */ 1472 #define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1473 #define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1474 #define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */ 1475 #define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1476 /* MFG5_PWR_CON (0x10006000+0x31C) */ 1477 #define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */ 1478 #define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */ 1479 #define MFG5_PWR_ON_LSB (1U << 2) /* 1b */ 1480 #define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1481 #define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1482 #define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */ 1483 #define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1484 /* MFG6_PWR_CON (0x10006000+0x320) */ 1485 #define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */ 1486 #define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */ 1487 #define MFG6_PWR_ON_LSB (1U << 2) /* 1b */ 1488 #define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1489 #define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1490 #define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */ 1491 #define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1492 /* IFR_PWR_CON (0x10006000+0x324) */ 1493 #define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ 1494 #define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ 1495 #define IFR_PWR_ON_LSB (1U << 2) /* 1b */ 1496 #define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1497 #define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1498 #define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */ 1499 #define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1500 /* IFR_SUB_PWR_CON (0x10006000+0x328) */ 1501 #define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */ 1502 #define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */ 1503 #define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */ 1504 #define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1505 #define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1506 #define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */ 1507 #define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1508 /* DPY_PWR_CON (0x10006000+0x32C) */ 1509 #define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ 1510 #define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ 1511 #define DPY_PWR_ON_LSB (1U << 2) /* 1b */ 1512 #define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1513 #define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1514 #define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */ 1515 #define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1516 /* ISP_PWR_CON (0x10006000+0x330) */ 1517 #define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1518 #define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ 1519 #define ISP_PWR_ON_LSB (1U << 2) /* 1b */ 1520 #define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1521 #define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1522 #define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1523 #define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1524 /* ISP2_PWR_CON (0x10006000+0x334) */ 1525 #define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1526 #define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */ 1527 #define ISP2_PWR_ON_LSB (1U << 2) /* 1b */ 1528 #define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1529 #define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1530 #define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1531 #define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1532 /* IPE_PWR_CON (0x10006000+0x338) */ 1533 #define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */ 1534 #define IPE_PWR_ISO_LSB (1U << 1) /* 1b */ 1535 #define IPE_PWR_ON_LSB (1U << 2) /* 1b */ 1536 #define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1537 #define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1538 #define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */ 1539 #define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1540 /* VDE_PWR_CON (0x10006000+0x33C) */ 1541 #define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ 1542 #define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ 1543 #define VDE_PWR_ON_LSB (1U << 2) /* 1b */ 1544 #define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1545 #define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1546 #define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */ 1547 #define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1548 /* VDE2_PWR_CON (0x10006000+0x340) */ 1549 #define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1550 #define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */ 1551 #define VDE2_PWR_ON_LSB (1U << 2) /* 1b */ 1552 #define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1553 #define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1554 #define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1555 #define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1556 /* VEN_PWR_CON (0x10006000+0x344) */ 1557 #define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1558 #define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ 1559 #define VEN_PWR_ON_LSB (1U << 2) /* 1b */ 1560 #define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1561 #define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1562 #define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */ 1563 #define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1564 /* VEN_CORE1_PWR_CON (0x10006000+0x348) */ 1565 #define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1566 #define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ 1567 #define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ 1568 #define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1569 #define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1570 #define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1571 #define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1572 /* MDP_PWR_CON (0x10006000+0x34C) */ 1573 #define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1574 #define MDP_PWR_ISO_LSB (1U << 1) /* 1b */ 1575 #define MDP_PWR_ON_LSB (1U << 2) /* 1b */ 1576 #define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1577 #define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1578 #define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1579 #define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1580 /* DIS_PWR_CON (0x10006000+0x350) */ 1581 #define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ 1582 #define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ 1583 #define DIS_PWR_ON_LSB (1U << 2) /* 1b */ 1584 #define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1585 #define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1586 #define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */ 1587 #define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1588 /* AUDIO_PWR_CON (0x10006000+0x354) */ 1589 #define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */ 1590 #define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */ 1591 #define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */ 1592 #define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1593 #define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1594 #define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */ 1595 #define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1596 /* ADSP_PWR_CON (0x10006000+0x358) */ 1597 #define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1598 #define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */ 1599 #define ADSP_PWR_ON_LSB (1U << 2) /* 1b */ 1600 #define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1601 #define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1602 #define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1603 #define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1604 #define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1605 #define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ 1606 #define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1607 #define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ 1608 /* CAM_PWR_CON (0x10006000+0x35C) */ 1609 #define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ 1610 #define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ 1611 #define CAM_PWR_ON_LSB (1U << 2) /* 1b */ 1612 #define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1613 #define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1614 #define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */ 1615 #define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1616 /* CAM_RAWA_PWR_CON (0x10006000+0x360) */ 1617 #define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */ 1618 #define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */ 1619 #define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */ 1620 #define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1621 #define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1622 #define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */ 1623 #define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1624 /* CAM_RAWB_PWR_CON (0x10006000+0x364) */ 1625 #define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */ 1626 #define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */ 1627 #define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */ 1628 #define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1629 #define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1630 #define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */ 1631 #define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1632 /* CAM_RAWC_PWR_CON (0x10006000+0x368) */ 1633 #define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1634 #define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */ 1635 #define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */ 1636 #define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1637 #define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1638 #define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */ 1639 #define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1640 /* SYSRAM_CON (0x10006000+0x36C) */ 1641 #define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1642 #define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1643 #define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */ 1644 #define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */ 1645 /* SYSROM_CON (0x10006000+0x370) */ 1646 #define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */ 1647 /* SSPM_SRAM_CON (0x10006000+0x374) */ 1648 #define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1649 #define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1650 #define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1651 #define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ 1652 /* SCP_SRAM_CON (0x10006000+0x378) */ 1653 #define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1654 #define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1655 #define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1656 #define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ 1657 /* DPY_SHU_SRAM_CON (0x10006000+0x37C) */ 1658 #define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1659 #define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1660 #define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ 1661 #define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */ 1662 /* UFS_SRAM_CON (0x10006000+0x380) */ 1663 #define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1664 #define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1665 #define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ 1666 #define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ 1667 /* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */ 1668 #define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1669 #define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1670 #define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1671 #define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */ 1672 /* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */ 1673 #define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1674 #define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1675 #define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1676 #define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */ 1677 /* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */ 1678 #define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1679 #define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1680 #define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1681 #define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */ 1682 /* USB_SRAM_CON (0x10006000+0x390) */ 1683 #define USB_SRAM_PDN_LSB (1U << 0) /* 7b */ 1684 /* DUMMY_SRAM_CON (0x10006000+0x394) */ 1685 #define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1686 #define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1687 #define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1688 #define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ 1689 /* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */ 1690 #define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1691 #define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1692 /* EXT_BUCK_ISO (0x10006000+0x39C) */ 1693 #define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1694 #define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1695 #define ADSP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ 1696 #define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */ 1697 /* DXCC_SRAM_CON (0x10006000+0x3A0) */ 1698 #define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1699 #define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1700 #define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1701 #define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */ 1702 /* MSDC_SRAM_CON (0x10006000+0x3A4) */ 1703 #define MSDC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1704 #define MSDC_PWR_ISO_LSB (1U << 1) /* 1b */ 1705 #define MSDC_PWR_ON_LSB (1U << 2) /* 1b */ 1706 #define MSDC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1707 #define MSDC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1708 #define MSDC_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1709 #define MSDC_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1710 #define MSDC_SRAM_PDN_LSB (1U << 8) /* 1b */ 1711 #define MSDC_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ 1712 #define SC_MSDC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1713 #define SC_MSDC_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ 1714 /* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */ 1715 #define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */ 1716 /* DP_TX_PWR_CON (0x10006000+0x3AC) */ 1717 #define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */ 1718 #define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */ 1719 #define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */ 1720 #define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1721 #define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1722 #define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */ 1723 #define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1724 /* DPMAIF_SRAM_CON (0x10006000+0x3B0) */ 1725 #define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1726 #define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1727 #define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1728 #define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */ 1729 /* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */ 1730 #define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1731 #define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1732 #define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ 1733 #define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */ 1734 /* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */ 1735 #define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1736 #define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1737 #define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1738 #define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */ 1739 /* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */ 1740 #define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1741 #define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1742 #define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1743 #define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */ 1744 /* MCUPM_SRAM_CON (0x10006000+0x3C0) */ 1745 #define MCUPM_PWR_RST_B_LSB (1U << 0) /* 1b */ 1746 #define MCUPM_PWR_ISO_LSB (1U << 1) /* 1b */ 1747 #define MCUPM_PWR_ON_LSB (1U << 2) /* 1b */ 1748 #define MCUPM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1749 #define MCUPM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1750 #define MCUPM_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1751 #define MCUPM_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1752 #define MCUPM_SRAM_PDN_LSB (1U << 8) /* 1b */ 1753 #define MCUPM_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ 1754 #define SC_MCUPM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1755 #define SC_MCUPM_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ 1756 /* DPY2_PWR_CON (0x10006000+0x3C4) */ 1757 #define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1758 #define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */ 1759 #define DPY2_PWR_ON_LSB (1U << 2) /* 1b */ 1760 #define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1761 #define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1762 #define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1763 #define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1764 /* PERI_PWR_CON (0x10006000+0x3C8) */ 1765 #define PERI_PWR_RST_B_LSB (1U << 0) /* 1b */ 1766 #define PERI_PWR_ISO_LSB (1U << 1) /* 1b */ 1767 #define PERI_PWR_ON_LSB (1U << 2) /* 1b */ 1768 #define PERI_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1769 #define PERI_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1770 #define PERI_SRAM_PDN_LSB (1U << 8) /* 1b */ 1771 #define SC_PERI_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1772 /* SPM_MEM_CK_SEL (0x10006000+0x400) */ 1773 #define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */ 1774 #define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */ 1775 /* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */ 1776 #define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */ 1777 /* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */ 1778 #define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */ 1779 /* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */ 1780 #define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */ 1781 /* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */ 1782 #define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */ 1783 /* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */ 1784 #define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */ 1785 /* SPM_EMI_BW_MODE (0x10006000+0x418) */ 1786 #define EMI_BW_MODE_LSB (1U << 0) /* 1b */ 1787 #define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ 1788 #define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ 1789 #define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ 1790 /* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */ 1791 #define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ 1792 /* ULPOSC_CON (0x10006000+0x420) */ 1793 #define ULPOSC_EN_LSB (1U << 0) /* 1b */ 1794 #define ULPOSC_RST_LSB (1U << 1) /* 1b */ 1795 #define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ 1796 #define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ 1797 /* SPM2MM_CON (0x10006000+0x424) */ 1798 #define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ 1799 #define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ 1800 #define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ 1801 #define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ 1802 #define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ 1803 #define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */ 1804 #define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */ 1805 #define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ 1806 #define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ 1807 #define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ 1808 /* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */ 1809 #define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */ 1810 /* SPM2MCUPM_CON (0x10006000+0x42C) */ 1811 #define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */ 1812 #define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */ 1813 /* AP_MDSRC_REQ (0x10006000+0x430) */ 1814 #define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ 1815 #define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ 1816 #define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ 1817 #define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ 1818 #define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ 1819 #define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ 1820 /* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */ 1821 #define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ 1822 /* SPM2MD_DVFS_CON (0x10006000+0x438) */ 1823 #define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ 1824 /* MD2SPM_DVFS_CON (0x10006000+0x43C) */ 1825 #define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 1826 /* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */ 1827 #define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */ 1828 /* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */ 1829 #define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */ 1830 /* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */ 1831 #define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */ 1832 /* SPM_PLL_CON (0x10006000+0x44C) */ 1833 #define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ 1834 #define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ 1835 #define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ 1836 #define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ 1837 #define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ 1838 #define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ 1839 #define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ 1840 #define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ 1841 #define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */ 1842 #define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */ 1843 /* CPU_DVFS_REQ (0x10006000+0x450) */ 1844 #define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ 1845 /* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */ 1846 #define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */ 1847 #define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */ 1848 /* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */ 1849 #define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */ 1850 /* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */ 1851 #define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */ 1852 /* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */ 1853 #define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */ 1854 /* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */ 1855 #define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */ 1856 /* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */ 1857 #define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */ 1858 #define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */ 1859 /* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */ 1860 #define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */ 1861 /* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */ 1862 #define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */ 1863 /* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */ 1864 #define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */ 1865 #define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */ 1866 #define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */ 1867 #define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */ 1868 #define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */ 1869 #define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */ 1870 /* RELAY_DVFS_LEVEL (0x10006000+0x478) */ 1871 #define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1872 /* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */ 1873 #define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */ 1874 #define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */ 1875 #define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */ 1876 #define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */ 1877 #define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */ 1878 #define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */ 1879 #define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */ 1880 #define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */ 1881 #define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */ 1882 #define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */ 1883 #define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */ 1884 #define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */ 1885 #define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */ 1886 #define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */ 1887 #define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */ 1888 /* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */ 1889 #define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */ 1890 #define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */ 1891 #define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */ 1892 #define SW_DMYRD_EN_LSB (1U << 6) /* 2b */ 1893 #define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */ 1894 #define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */ 1895 #define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */ 1896 #define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */ 1897 #define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */ 1898 #define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */ 1899 #define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */ 1900 #define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */ 1901 #define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */ 1902 #define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */ 1903 /* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */ 1904 #define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */ 1905 #define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */ 1906 #define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */ 1907 #define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */ 1908 #define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */ 1909 #define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */ 1910 #define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */ 1911 #define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */ 1912 #define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */ 1913 #define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */ 1914 #define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */ 1915 /* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */ 1916 #define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */ 1917 #define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */ 1918 #define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */ 1919 #define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */ 1920 #define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */ 1921 #define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */ 1922 #define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */ 1923 #define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */ 1924 /* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */ 1925 #define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */ 1926 #define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */ 1927 #define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */ 1928 #define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */ 1929 #define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */ 1930 #define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */ 1931 #define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */ 1932 #define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */ 1933 #define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */ 1934 #define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */ 1935 #define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */ 1936 #define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */ 1937 #define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */ 1938 #define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */ 1939 #define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */ 1940 /* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */ 1941 #define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */ 1942 #define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */ 1943 #define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */ 1944 #define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */ 1945 #define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */ 1946 #define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */ 1947 #define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */ 1948 #define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */ 1949 #define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */ 1950 #define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */ 1951 #define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */ 1952 #define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */ 1953 #define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */ 1954 /* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */ 1955 #define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */ 1956 #define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */ 1957 #define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */ 1958 #define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */ 1959 #define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */ 1960 #define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */ 1961 #define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */ 1962 #define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */ 1963 #define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */ 1964 #define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */ 1965 #define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */ 1966 /* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */ 1967 #define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */ 1968 #define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */ 1969 #define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */ 1970 #define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */ 1971 #define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */ 1972 #define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */ 1973 #define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */ 1974 #define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */ 1975 /* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */ 1976 #define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */ 1977 #define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */ 1978 #define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */ 1979 #define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */ 1980 #define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */ 1981 #define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */ 1982 #define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */ 1983 #define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */ 1984 #define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */ 1985 #define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */ 1986 #define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */ 1987 #define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */ 1988 #define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */ 1989 #define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */ 1990 #define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */ 1991 #define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */ 1992 #define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */ 1993 #define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */ 1994 #define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */ 1995 #define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */ 1996 #define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */ 1997 #define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */ 1998 /* SPM_DVFS_LEVEL (0x10006000+0x4A4) */ 1999 #define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 2000 /* SPM_CIRQ_CON (0x10006000+0x4A8) */ 2001 #define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */ 2002 /* SPM_DVFS_MISC (0x10006000+0x4AC) */ 2003 #define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ 2004 #define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */ 2005 #define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ 2006 #define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */ 2007 #define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ 2008 #define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */ 2009 #define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */ 2010 #define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */ 2011 #define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */ 2012 #define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */ 2013 /* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */ 2014 #define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */ 2015 #define VS1_INIT_LSB (1U << 2) /* 1b */ 2016 #define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */ 2017 #define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */ 2018 #define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */ 2019 #define VS1_TRIGGER_LSB (1U << 9) /* 1b */ 2020 #define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */ 2021 #define VS2_INIT_LSB (1U << 13) /* 1b */ 2022 #define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */ 2023 #define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */ 2024 #define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */ 2025 #define VS2_TRIGGER_LSB (1U << 23) /* 1b */ 2026 #define VS1_FORCE_LSB (1U << 24) /* 1b */ 2027 #define VS2_FORCE_LSB (1U << 25) /* 1b */ 2028 #define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */ 2029 #define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */ 2030 /* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */ 2031 #define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2032 /* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */ 2033 #define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2034 /* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */ 2035 #define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2036 /* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */ 2037 #define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2038 /* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */ 2039 #define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2040 /* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */ 2041 #define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2042 /* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */ 2043 #define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2044 /* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */ 2045 #define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2046 /* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */ 2047 #define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2048 /* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */ 2049 #define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2050 /* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */ 2051 #define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2052 /* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */ 2053 #define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2054 /* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */ 2055 #define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2056 /* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */ 2057 #define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2058 /* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */ 2059 #define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2060 /* SPM_CG_CHECK_CON (0x10006000+0x4F0) */ 2061 #define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */ 2062 #define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */ 2063 #define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */ 2064 #define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */ 2065 #define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */ 2066 #define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */ 2067 #define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */ 2068 #define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */ 2069 #define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */ 2070 /* SPM_SRC_RDY_STA (0x10006000+0x4F4) */ 2071 #define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */ 2072 #define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */ 2073 /* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */ 2074 #define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */ 2075 #define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */ 2076 /* SPM_FORCE_DVFS (0x10006000+0x4FC) */ 2077 #define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 2078 /* SRCLKEN_RC_CFG (0x10006000+0x500) */ 2079 #define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */ 2080 /* RC_CENTRAL_CFG1 (0x10006000+0x504) */ 2081 #define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */ 2082 /* RC_CENTRAL_CFG2 (0x10006000+0x508) */ 2083 #define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */ 2084 /* RC_CMD_ARB_CFG (0x10006000+0x50C) */ 2085 #define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */ 2086 /* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */ 2087 #define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */ 2088 #define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */ 2089 /* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */ 2090 #define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */ 2091 #define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */ 2092 /* RC_DCXO_FPM_CFG (0x10006000+0x518) */ 2093 #define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */ 2094 /* RC_CENTRAL_CFG3 (0x10006000+0x51C) */ 2095 #define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */ 2096 /* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */ 2097 #define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2098 #define RC_SW_SRCLKEN_RC (1U << 3) /* 1b */ 2099 #define RC_SW_SRCLKEN_FPM (1U << 4) /* 1b */ 2100 /* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */ 2101 #define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2102 /* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */ 2103 #define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2104 /* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */ 2105 #define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2106 /* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */ 2107 #define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2108 /* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */ 2109 #define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2110 /* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */ 2111 #define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2112 /* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */ 2113 #define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2114 /* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */ 2115 #define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2116 /* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */ 2117 #define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2118 /* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */ 2119 #define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2120 /* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */ 2121 #define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2122 /* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */ 2123 #define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2124 /* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */ 2125 #define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */ 2126 /* RC_CENTRAL_CFG4 (0x10006000+0x558) */ 2127 #define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */ 2128 /* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */ 2129 #define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */ 2130 /* RC_DEBUG_CFG (0x10006000+0x564) */ 2131 #define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */ 2132 /* RC_MISC_0 (0x10006000+0x5B4) */ 2133 #define SRCCLKENO_LSB (1U << 0) /* 2b */ 2134 #define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */ 2135 #define RC_VREQ_LSB (1U << 5) /* 1b */ 2136 #define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */ 2137 /* RC_SPM_CTRL (0x10006000+0x5B8) */ 2138 #define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */ 2139 #define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */ 2140 #define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */ 2141 /* SUBSYS_INTF_CFG (0x10006000+0x5BC) */ 2142 #define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */ 2143 #define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */ 2144 /* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */ 2145 #define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */ 2146 /* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */ 2147 #define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */ 2148 /* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */ 2149 #define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */ 2150 /* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */ 2151 #define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */ 2152 /* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */ 2153 #define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */ 2154 /* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */ 2155 #define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */ 2156 /* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */ 2157 #define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */ 2158 /* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */ 2159 #define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */ 2160 /* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */ 2161 #define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */ 2162 /* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */ 2163 #define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */ 2164 /* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */ 2165 #define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */ 2166 /* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */ 2167 #define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */ 2168 /* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */ 2169 #define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */ 2170 /* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */ 2171 #define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */ 2172 /* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */ 2173 #define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */ 2174 /* SPM_SW_FLAG_0 (0x10006000+0x600) */ 2175 #define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ 2176 /* SPM_SW_DEBUG_0 (0x10006000+0x604) */ 2177 #define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */ 2178 /* SPM_SW_FLAG_1 (0x10006000+0x608) */ 2179 #define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */ 2180 /* SPM_SW_DEBUG_1 (0x10006000+0x60C) */ 2181 #define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */ 2182 /* SPM_SW_RSV_0 (0x10006000+0x610) */ 2183 #define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ 2184 /* SPM_SW_RSV_1 (0x10006000+0x614) */ 2185 #define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ 2186 /* SPM_SW_RSV_2 (0x10006000+0x618) */ 2187 #define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ 2188 /* SPM_SW_RSV_3 (0x10006000+0x61C) */ 2189 #define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ 2190 /* SPM_SW_RSV_4 (0x10006000+0x620) */ 2191 #define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ 2192 /* SPM_SW_RSV_5 (0x10006000+0x624) */ 2193 #define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ 2194 /* SPM_SW_RSV_6 (0x10006000+0x628) */ 2195 #define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ 2196 /* SPM_SW_RSV_7 (0x10006000+0x62C) */ 2197 #define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ 2198 /* SPM_SW_RSV_8 (0x10006000+0x630) */ 2199 #define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ 2200 /* SPM_BK_WAKE_EVENT (0x10006000+0x634) */ 2201 #define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */ 2202 /* SPM_BK_VTCXO_DUR (0x10006000+0x638) */ 2203 #define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */ 2204 /* SPM_BK_WAKE_MISC (0x10006000+0x63C) */ 2205 #define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */ 2206 /* SPM_BK_PCM_TIMER (0x10006000+0x640) */ 2207 #define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */ 2208 /* SPM_RSV_CON_0 (0x10006000+0x650) */ 2209 #define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */ 2210 /* SPM_RSV_CON_1 (0x10006000+0x654) */ 2211 #define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */ 2212 /* SPM_RSV_STA_0 (0x10006000+0x658) */ 2213 #define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */ 2214 /* SPM_RSV_STA_1 (0x10006000+0x65C) */ 2215 #define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */ 2216 /* SPM_SPARE_CON (0x10006000+0x660) */ 2217 #define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ 2218 /* SPM_SPARE_CON_SET (0x10006000+0x664) */ 2219 #define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 2220 /* SPM_SPARE_CON_CLR (0x10006000+0x668) */ 2221 #define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 2222 /* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */ 2223 #define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 5b */ 2224 #define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 8) /* 5b */ 2225 /* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */ 2226 #define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 5b */ 2227 #define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 8) /* 5b */ 2228 /* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */ 2229 #define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 5b */ 2230 #define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 8) /* 5b */ 2231 /* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */ 2232 #define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 5b */ 2233 #define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 8) /* 5b */ 2234 /* SCP_VCORE_LEVEL (0x10006000+0x67C) */ 2235 #define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */ 2236 /* SC_MM_CK_SEL_CON (0x10006000+0x680) */ 2237 #define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ 2238 #define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ 2239 /* SPARE_ACK_MASK (0x10006000+0x684) */ 2240 #define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ 2241 /* SPM_CROSS_WAKE_M04_REQ (0x10006000+0x688) */ 2242 #define SPM_CROSS_WAKE_M04_REQ_LSB (1U << 0) /* 5b */ 2243 #define SPM_CROSS_WAKE_M04_CHK_LSB (1U << 8) /* 5b */ 2244 /* SPM_DV_CON_0 (0x10006000+0x68C) */ 2245 #define SPM_DV_CON_0_LSB (1U << 0) /* 32b */ 2246 /* SPM_DV_CON_1 (0x10006000+0x690) */ 2247 #define SPM_DV_CON_1_LSB (1U << 0) /* 32b */ 2248 /* SPM_DV_STA (0x10006000+0x694) */ 2249 #define SPM_DV_STA_LSB (1U << 0) /* 32b */ 2250 /* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */ 2251 #define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */ 2252 /* SPM_SEMA_M0 (0x10006000+0x69C) */ 2253 #define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ 2254 /* SPM_SEMA_M1 (0x10006000+0x6A0) */ 2255 #define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ 2256 /* SPM_SEMA_M2 (0x10006000+0x6A4) */ 2257 #define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ 2258 /* SPM_SEMA_M3 (0x10006000+0x6A8) */ 2259 #define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ 2260 /* SPM_SEMA_M4 (0x10006000+0x6AC) */ 2261 #define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ 2262 /* SPM_SEMA_M5 (0x10006000+0x6B0) */ 2263 #define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ 2264 /* SPM_SEMA_M6 (0x10006000+0x6B4) */ 2265 #define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ 2266 /* SPM_SEMA_M7 (0x10006000+0x6B8) */ 2267 #define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ 2268 /* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */ 2269 #define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */ 2270 /* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */ 2271 #define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */ 2272 /* SPM_ADSP_IRQ (0x10006000+0x6C4) */ 2273 #define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */ 2274 #define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ 2275 /* SPM_MD32_IRQ (0x10006000+0x6C8) */ 2276 #define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */ 2277 #define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */ 2278 /* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */ 2279 #define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ 2280 /* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */ 2281 #define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ 2282 /* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */ 2283 #define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ 2284 /* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */ 2285 #define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ 2286 /* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */ 2287 #define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 2288 /* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */ 2289 #define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 2290 /* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */ 2291 #define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 2292 /* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */ 2293 #define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 2294 /* UFS_PSRI_SW (0x10006000+0x6EC) */ 2295 #define UFS_PSRI_SW_LSB (1U << 0) /* 1b */ 2296 /* UFS_PSRI_SW_SET (0x10006000+0x6F0) */ 2297 #define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */ 2298 /* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */ 2299 #define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */ 2300 /* SPM_AP_SEMA (0x10006000+0x6F8) */ 2301 #define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ 2302 /* SPM_SPM_SEMA (0x10006000+0x6FC) */ 2303 #define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ 2304 /* SPM_DVFS_CON (0x10006000+0x700) */ 2305 #define SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 2306 /* SPM_DVFS_CON_STA (0x10006000+0x704) */ 2307 #define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */ 2308 /* SPM_PMIC_SPMI_CON (0x10006000+0x708) */ 2309 #define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */ 2310 #define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */ 2311 #define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */ 2312 #define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */ 2313 /* SPM_DVFS_CMD0 (0x10006000+0x710) */ 2314 #define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ 2315 /* SPM_DVFS_CMD1 (0x10006000+0x714) */ 2316 #define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ 2317 /* SPM_DVFS_CMD2 (0x10006000+0x718) */ 2318 #define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ 2319 /* SPM_DVFS_CMD3 (0x10006000+0x71C) */ 2320 #define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ 2321 /* SPM_DVFS_CMD4 (0x10006000+0x720) */ 2322 #define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ 2323 /* SPM_DVFS_CMD5 (0x10006000+0x724) */ 2324 #define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ 2325 /* SPM_DVFS_CMD6 (0x10006000+0x728) */ 2326 #define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ 2327 /* SPM_DVFS_CMD7 (0x10006000+0x72C) */ 2328 #define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ 2329 /* SPM_DVFS_CMD8 (0x10006000+0x730) */ 2330 #define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ 2331 /* SPM_DVFS_CMD9 (0x10006000+0x734) */ 2332 #define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ 2333 /* SPM_DVFS_CMD10 (0x10006000+0x738) */ 2334 #define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ 2335 /* SPM_DVFS_CMD11 (0x10006000+0x73C) */ 2336 #define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ 2337 /* SPM_DVFS_CMD12 (0x10006000+0x740) */ 2338 #define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ 2339 /* SPM_DVFS_CMD13 (0x10006000+0x744) */ 2340 #define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ 2341 /* SPM_DVFS_CMD14 (0x10006000+0x748) */ 2342 #define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ 2343 /* SPM_DVFS_CMD15 (0x10006000+0x74C) */ 2344 #define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ 2345 /* SPM_DVFS_CMD16 (0x10006000+0x750) */ 2346 #define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */ 2347 /* SPM_DVFS_CMD17 (0x10006000+0x754) */ 2348 #define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */ 2349 /* SPM_DVFS_CMD18 (0x10006000+0x758) */ 2350 #define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */ 2351 /* SPM_DVFS_CMD19 (0x10006000+0x75C) */ 2352 #define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */ 2353 /* SPM_DVFS_CMD20 (0x10006000+0x760) */ 2354 #define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */ 2355 /* SPM_DVFS_CMD21 (0x10006000+0x764) */ 2356 #define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */ 2357 /* SPM_DVFS_CMD22 (0x10006000+0x768) */ 2358 #define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */ 2359 /* SPM_DVFS_CMD23 (0x10006000+0x76C) */ 2360 #define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */ 2361 /* SYS_TIMER_VALUE_L (0x10006000+0x770) */ 2362 #define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */ 2363 /* SYS_TIMER_VALUE_H (0x10006000+0x774) */ 2364 #define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */ 2365 /* SYS_TIMER_START_L (0x10006000+0x778) */ 2366 #define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */ 2367 /* SYS_TIMER_START_H (0x10006000+0x77C) */ 2368 #define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */ 2369 /* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */ 2370 #define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ 2371 /* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */ 2372 #define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ 2373 /* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */ 2374 #define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ 2375 /* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */ 2376 #define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ 2377 /* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */ 2378 #define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ 2379 /* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */ 2380 #define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ 2381 /* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */ 2382 #define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ 2383 /* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */ 2384 #define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ 2385 /* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */ 2386 #define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ 2387 /* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */ 2388 #define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ 2389 /* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */ 2390 #define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ 2391 /* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */ 2392 #define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ 2393 /* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */ 2394 #define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ 2395 /* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */ 2396 #define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ 2397 /* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */ 2398 #define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ 2399 /* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */ 2400 #define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ 2401 /* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */ 2402 #define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */ 2403 /* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */ 2404 #define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */ 2405 /* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */ 2406 #define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */ 2407 /* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */ 2408 #define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */ 2409 /* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */ 2410 #define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */ 2411 /* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */ 2412 #define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */ 2413 /* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */ 2414 #define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */ 2415 /* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */ 2416 #define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */ 2417 /* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */ 2418 #define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */ 2419 /* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */ 2420 #define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */ 2421 /* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */ 2422 #define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */ 2423 /* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */ 2424 #define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */ 2425 /* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */ 2426 #define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */ 2427 /* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */ 2428 #define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */ 2429 /* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */ 2430 #define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */ 2431 /* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */ 2432 #define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */ 2433 /* PCM_WDT_LATCH_0 (0x10006000+0x800) */ 2434 #define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ 2435 /* PCM_WDT_LATCH_1 (0x10006000+0x804) */ 2436 #define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ 2437 /* PCM_WDT_LATCH_2 (0x10006000+0x808) */ 2438 #define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ 2439 /* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ 2440 #define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ 2441 /* PCM_WDT_LATCH_4 (0x10006000+0x810) */ 2442 #define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ 2443 /* PCM_WDT_LATCH_5 (0x10006000+0x814) */ 2444 #define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ 2445 /* PCM_WDT_LATCH_6 (0x10006000+0x818) */ 2446 #define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ 2447 /* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ 2448 #define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ 2449 /* PCM_WDT_LATCH_8 (0x10006000+0x820) */ 2450 #define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ 2451 /* PCM_WDT_LATCH_9 (0x10006000+0x824) */ 2452 #define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ 2453 /* PCM_WDT_LATCH_10 (0x10006000+0x828) */ 2454 #define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ 2455 /* PCM_WDT_LATCH_11 (0x10006000+0x82C) */ 2456 #define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ 2457 /* PCM_WDT_LATCH_12 (0x10006000+0x830) */ 2458 #define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ 2459 /* PCM_WDT_LATCH_13 (0x10006000+0x834) */ 2460 #define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ 2461 /* PCM_WDT_LATCH_14 (0x10006000+0x838) */ 2462 #define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */ 2463 /* PCM_WDT_LATCH_15 (0x10006000+0x83C) */ 2464 #define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */ 2465 /* PCM_WDT_LATCH_16 (0x10006000+0x840) */ 2466 #define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */ 2467 /* PCM_WDT_LATCH_17 (0x10006000+0x844) */ 2468 #define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */ 2469 /* PCM_WDT_LATCH_18 (0x10006000+0x848) */ 2470 #define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */ 2471 /* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */ 2472 #define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ 2473 /* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */ 2474 #define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */ 2475 /* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */ 2476 #define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */ 2477 /* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */ 2478 #define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */ 2479 /* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */ 2480 #define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */ 2481 /* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */ 2482 #define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */ 2483 /* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */ 2484 #define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */ 2485 /* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */ 2486 #define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */ 2487 /* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */ 2488 #define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */ 2489 /* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */ 2490 #define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */ 2491 /* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */ 2492 #define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */ 2493 /* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */ 2494 #define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */ 2495 /* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */ 2496 #define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */ 2497 /* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */ 2498 #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ 2499 /* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */ 2500 #define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */ 2501 #define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */ 2502 #define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */ 2503 #define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */ 2504 #define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */ 2505 #define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */ 2506 #define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */ 2507 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */ 2508 #define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */ 2509 #define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */ 2510 #define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */ 2511 /* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */ 2512 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */ 2513 #define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */ 2514 /* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */ 2515 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */ 2516 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */ 2517 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */ 2518 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */ 2519 /* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */ 2520 #define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */ 2521 #define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */ 2522 /* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */ 2523 #define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */ 2524 /* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */ 2525 #define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */ 2526 /* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */ 2527 #define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */ 2528 #define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */ 2529 #define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */ 2530 #define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */ 2531 #define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */ 2532 #define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */ 2533 #define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */ 2534 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */ 2535 #define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */ 2536 #define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */ 2537 #define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */ 2538 /* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */ 2539 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */ 2540 #define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */ 2541 /* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */ 2542 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */ 2543 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */ 2544 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */ 2545 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */ 2546 /* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */ 2547 #define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */ 2548 #define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */ 2549 /* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */ 2550 #define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */ 2551 /* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */ 2552 #define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */ 2553 /* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */ 2554 #define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */ 2555 #define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */ 2556 #define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */ 2557 #define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */ 2558 #define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */ 2559 #define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */ 2560 #define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */ 2561 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */ 2562 #define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */ 2563 #define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */ 2564 #define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */ 2565 /* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */ 2566 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */ 2567 #define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */ 2568 /* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */ 2569 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */ 2570 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */ 2571 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */ 2572 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */ 2573 /* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */ 2574 #define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */ 2575 #define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */ 2576 /* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */ 2577 #define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */ 2578 /* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */ 2579 #define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */ 2580 /* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */ 2581 #define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */ 2582 #define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */ 2583 #define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */ 2584 #define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */ 2585 #define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */ 2586 #define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */ 2587 #define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */ 2588 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */ 2589 #define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */ 2590 #define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */ 2591 #define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */ 2592 /* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */ 2593 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */ 2594 #define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */ 2595 /* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */ 2596 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */ 2597 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */ 2598 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */ 2599 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */ 2600 /* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */ 2601 #define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */ 2602 #define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */ 2603 /* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */ 2604 #define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */ 2605 /* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */ 2606 #define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */ 2607 /* SPM_COUNTER_0 (0x10006000+0x978) */ 2608 #define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */ 2609 #define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */ 2610 #define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */ 2611 #define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */ 2612 #define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */ 2613 #define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */ 2614 /* SPM_COUNTER_1 (0x10006000+0x97C) */ 2615 #define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */ 2616 #define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */ 2617 #define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */ 2618 #define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */ 2619 #define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */ 2620 #define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */ 2621 /* SPM_COUNTER_2 (0x10006000+0x980) */ 2622 #define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */ 2623 #define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */ 2624 #define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */ 2625 #define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */ 2626 #define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */ 2627 #define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */ 2628 /* SYS_TIMER_CON (0x10006000+0x98C) */ 2629 #define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ 2630 #define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */ 2631 #define SYS_TIMER_ID_LSB (1U << 8) /* 8b */ 2632 #define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */ 2633 /* RC_FSM_STA_0 (0x10006000+0xE00) */ 2634 #define RC_FSM_STA_0_LSB (1U << 0) /* 32b */ 2635 /* RC_CMD_STA_0 (0x10006000+0xE04) */ 2636 #define RC_CMD_STA_0_LSB (1U << 0) /* 32b */ 2637 /* RC_CMD_STA_1 (0x10006000+0xE08) */ 2638 #define RC_CMD_STA_1_LSB (1U << 0) /* 32b */ 2639 /* RC_SPI_STA_0 (0x10006000+0xE0C) */ 2640 #define RC_SPI_STA_0_LSB (1U << 0) /* 32b */ 2641 /* RC_PI_PO_STA_0 (0x10006000+0xE10) */ 2642 #define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */ 2643 /* RC_M00_REQ_STA_0 (0x10006000+0xE14) */ 2644 #define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */ 2645 /* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */ 2646 #define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */ 2647 /* RC_M02_REQ_STA_0 (0x10006000+0xE20) */ 2648 #define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */ 2649 /* RC_M03_REQ_STA_0 (0x10006000+0xE24) */ 2650 #define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */ 2651 /* RC_M04_REQ_STA_0 (0x10006000+0xE28) */ 2652 #define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */ 2653 /* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */ 2654 #define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */ 2655 /* RC_M06_REQ_STA_0 (0x10006000+0xE30) */ 2656 #define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */ 2657 /* RC_M07_REQ_STA_0 (0x10006000+0xE34) */ 2658 #define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */ 2659 /* RC_M08_REQ_STA_0 (0x10006000+0xE38) */ 2660 #define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */ 2661 /* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */ 2662 #define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */ 2663 /* RC_M10_REQ_STA_0 (0x10006000+0xE40) */ 2664 #define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */ 2665 /* RC_M11_REQ_STA_0 (0x10006000+0xE44) */ 2666 #define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */ 2667 /* RC_M12_REQ_STA_0 (0x10006000+0xE48) */ 2668 #define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */ 2669 /* RC_DEBUG_STA_0 (0x10006000+0xE4C) */ 2670 #define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */ 2671 /* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */ 2672 #define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */ 2673 /* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */ 2674 #define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */ 2675 /* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */ 2676 #define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */ 2677 /* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */ 2678 #define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */ 2679 /* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */ 2680 #define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */ 2681 /* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */ 2682 #define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */ 2683 /* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */ 2684 #define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */ 2685 /* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */ 2686 #define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */ 2687 /* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */ 2688 #define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */ 2689 /* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */ 2690 #define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */ 2691 /* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */ 2692 #define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */ 2693 /* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */ 2694 #define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */ 2695 /* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */ 2696 #define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */ 2697 /* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */ 2698 #define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */ 2699 /* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */ 2700 #define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */ 2701 /* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */ 2702 #define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */ 2703 /* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */ 2704 #define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ 2705 /* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */ 2706 #define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ 2707 /* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */ 2708 #define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ 2709 /* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */ 2710 #define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ 2711 /* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */ 2712 #define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ 2713 /* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */ 2714 #define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ 2715 /* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */ 2716 #define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ 2717 /* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */ 2718 #define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ 2719 /* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */ 2720 #define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ 2721 /* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */ 2722 #define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ 2723 /* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */ 2724 #define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ 2725 /* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */ 2726 #define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ 2727 /* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */ 2728 #define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ 2729 /* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */ 2730 #define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ 2731 /* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */ 2732 #define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ 2733 /* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */ 2734 #define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ 2735 /* PCM_WDT_LATCH_19 (0x10006000+0xED8) */ 2736 #define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */ 2737 /* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */ 2738 #define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */ 2739 /* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */ 2740 #define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */ 2741 /* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */ 2742 #define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */ 2743 /* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */ 2744 #define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */ 2745 /* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */ 2746 #define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */ 2747 /* PMSR_LAST_DAT (0x10006000+0xF00) */ 2748 #define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */ 2749 /* PMSR_LAST_CNT (0x10006000+0xF04) */ 2750 #define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */ 2751 #define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */ 2752 /* PMSR_LAST_ACK (0x10006000+0xF08) */ 2753 #define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */ 2754 /* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */ 2755 #define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */ 2756 #define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */ 2757 #define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */ 2758 #define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */ 2759 /* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */ 2760 #define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */ 2761 #define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */ 2762 #define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */ 2763 #define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */ 2764 /* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */ 2765 #define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */ 2766 #define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */ 2767 #define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */ 2768 #define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */ 2769 /* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */ 2770 #define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */ 2771 #define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */ 2772 #define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */ 2773 #define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */ 2774 /* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */ 2775 #define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */ 2776 #define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */ 2777 #define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */ 2778 #define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */ 2779 /* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */ 2780 #define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */ 2781 #define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */ 2782 #define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */ 2783 #define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */ 2784 /* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */ 2785 #define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */ 2786 #define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */ 2787 #define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */ 2788 #define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */ 2789 /* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */ 2790 #define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */ 2791 #define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */ 2792 #define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */ 2793 #define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */ 2794 /* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */ 2795 #define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */ 2796 #define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */ 2797 #define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */ 2798 #define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */ 2799 /* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */ 2800 #define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */ 2801 #define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */ 2802 #define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */ 2803 #define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */ 2804 /* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */ 2805 #define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */ 2806 #define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */ 2807 #define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */ 2808 #define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */ 2809 /* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */ 2810 #define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */ 2811 #define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */ 2812 #define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */ 2813 #define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */ 2814 /* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */ 2815 #define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */ 2816 /* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */ 2817 #define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */ 2818 /* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */ 2819 #define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */ 2820 /* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */ 2821 #define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */ 2822 #define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */ 2823 #define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */ 2824 #define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */ 2825 #define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */ 2826 #define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */ 2827 #define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */ 2828 #define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */ 2829 #define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */ 2830 #define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */ 2831 #define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */ 2832 #define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */ 2833 #define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */ 2834 #define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */ 2835 #define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */ 2836 #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */ 2837 #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */ 2838 #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */ 2839 #define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */ 2840 #define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */ 2841 #define PMSR_MODE_LSB (1U << 20) /* 2b */ 2842 #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */ 2843 #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */ 2844 #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */ 2845 /* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */ 2846 #define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */ 2847 /* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */ 2848 #define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */ 2849 /* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */ 2850 #define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */ 2851 /* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */ 2852 #define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */ 2853 /* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */ 2854 #define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */ 2855 /* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */ 2856 #define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */ 2857 #define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */ 2858 #define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */ 2859 /* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */ 2860 #define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */ 2861 #define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */ 2862 #define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */ 2863 #define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */ 2864 #define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */ 2865 #define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */ 2866 #define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */ 2867 #define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */ 2868 #define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */ 2869 #define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */ 2870 #define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */ 2871 #define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */ 2872 #define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */ 2873 #define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */ 2874 #define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */ 2875 #define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */ 2876 /* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */ 2877 #define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */ 2878 #define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */ 2879 #define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */ 2880 #define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */ 2881 #define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */ 2882 #define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */ 2883 #define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */ 2884 #define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */ 2885 #define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */ 2886 #define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */ 2887 #define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */ 2888 #define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */ 2889 #define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */ 2890 #define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */ 2891 #define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */ 2892 #define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */ 2893 /* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */ 2894 #define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */ 2895 #define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */ 2896 #define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */ 2897 #define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */ 2898 #define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */ 2899 #define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */ 2900 #define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */ 2901 #define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */ 2902 #define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */ 2903 #define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */ 2904 #define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */ 2905 #define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */ 2906 #define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */ 2907 #define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */ 2908 #define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */ 2909 #define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */ 2910 /* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */ 2911 #define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */ 2912 /* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */ 2913 #define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */ 2914 /* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */ 2915 #define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */ 2916 2917 #define SPM_PROJECT_CODE 0xb16 2918 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 2919 #endif /* MT_SPM_REG */ 2920
