1 /*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <arch.h>
9 #include <common/bl_common.h>
10 #include <common/debug.h>
11 #include <drivers/delay_timer.h>
12 #include <drivers/generic_delay_timer.h>
13 #if XLAT_TABLES_LIB_V2 && PLAT_XLAT_TABLES_DYNAMIC
14 #include <lib/xlat_tables/xlat_tables_v2.h>
15 #endif
16 #include <plat/common/platform.h>
17
18 #if COREBOOT
19 #include <common/desc_image_load.h>
20
21 #include <drivers/ti/uart/uart_16550.h>
22 #include <lib/coreboot.h>
23 #include <plat_params.h>
24 #endif
25
26 /* MTK headers */
27 #if MTK_SIP_KERNEL_BOOT_ENABLE
28 #include <cold_boot.h>
29 #endif
30 #include <lib/mtk_init/mtk_init.h>
31 #include <mtk_mmap_pool.h>
32
33 IMPORT_SYM(uintptr_t, __RW_START__, RW_START);
34 IMPORT_SYM(uintptr_t, __DATA_START__, DATA_START);
35
36 #if COREBOOT
37 static entry_point_info_t bl32_ep_info;
38 static entry_point_info_t bl33_ep_info;
39
40 /*******************************************************************************
41 * Return a pointer to the 'entry_point_info' structure of the next image for
42 * the security state specified. BL33 corresponds to the non-secure image type
43 * while BL32 corresponds to the secure image type. A NULL pointer is returned
44 * if the image does not exist.
45 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)46 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
47 {
48 entry_point_info_t *next_image_info;
49
50 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
51 assert(next_image_info->h.type == PARAM_EP);
52
53 /* None of the images on this platform can have 0x0 as the entrypoint */
54 if (next_image_info->pc) {
55 return next_image_info;
56 } else {
57 return NULL;
58 }
59 }
60 #else
61 #ifndef MTK_BL31_AS_BL2
62 static struct mtk_bl31_fw_config bl31_fw_config;
63 #else
64 struct mtk_bl31_fw_config bl31_fw_config;
65 #endif
66 /* In order to be accessed after MMU enable */
67 static struct mtk_bl_param_t bl_param_clone;
68
get_mtk_bl31_fw_config(int index)69 void *get_mtk_bl31_fw_config(int index)
70 {
71 void *arg = NULL;
72
73 switch (index) {
74 case BOOT_ARG_FROM_BL2:
75 arg = bl31_fw_config.from_bl2;
76 break;
77 case BOOT_ARG_SOC_FW_CONFIG:
78 arg = bl31_fw_config.soc_fw_config;
79 break;
80 case BOOT_ARG_HW_CONFIG:
81 arg = bl31_fw_config.hw_config;
82 break;
83 case BOOT_ARG_RESERVED:
84 arg = bl31_fw_config.reserved;
85 break;
86 default:
87 WARN("Fail to get boot arg, index:%d", index);
88 break;
89 }
90 return arg;
91 }
92 #endif
93 /*****************************************************************************
94 * Perform the very early platform specific architectural setup shared between
95 * ARM standard platforms. This only does basic initialization. Later
96 * architectural setup (bl31_arch_setup()) does not do anything platform
97 * specific.
98 ******************************************************************************/
bl31_early_platform_setup2(u_register_t from_bl2,u_register_t soc_fw_config,u_register_t hw_config,u_register_t plat_params_from_bl2)99 void bl31_early_platform_setup2(u_register_t from_bl2,
100 u_register_t soc_fw_config,
101 u_register_t hw_config, u_register_t plat_params_from_bl2)
102
103 {
104 #if COREBOOT
105 static console_t console;
106
107 params_early_setup(soc_fw_config);
108 if (coreboot_serial.type) {
109 console_16550_register(coreboot_serial.baseaddr,
110 coreboot_serial.input_hertz,
111 coreboot_serial.baud,
112 &console);
113 }
114 bl31_params_parse_helper(from_bl2, &bl32_ep_info, &bl33_ep_info);
115 #else
116 struct mtk_bl_param_t *p_mtk_bl_param = (struct mtk_bl_param_t *)from_bl2;
117
118 if (p_mtk_bl_param == NULL) {
119 ERROR("from_bl2 should not be NULL\n");
120 panic();
121 }
122 memcpy(&bl_param_clone, p_mtk_bl_param, sizeof(struct mtk_bl_param_t));
123 bl31_fw_config.from_bl2 = (void *)&bl_param_clone;
124 bl31_fw_config.soc_fw_config = (void *)soc_fw_config;
125 bl31_fw_config.hw_config = (void *)hw_config;
126 bl31_fw_config.reserved = (void *)plat_params_from_bl2;
127 #endif
128
129 INFO("MTK BL31 start\n");
130 /* Init delay function */
131 generic_delay_timer_init();
132 /* Initialize module initcall */
133 mtk_init_one_level(MTK_INIT_LVL_EARLY_PLAT);
134 }
135
bl31_plat_arch_setup(void)136 void bl31_plat_arch_setup(void)
137 {
138 const mmap_region_t bl_regions[] = {
139 MAP_BL_RO,
140 MAP_BL_RW,
141 #if USE_COHERENT_MEM
142 MAP_BL_COHERENT_RAM,
143 #endif
144 {0},
145 };
146
147 mtk_xlat_init(bl_regions);
148 /* Initialize module initcall */
149 mtk_init_one_level(MTK_INIT_LVL_ARCH);
150 }
151
152 /*****************************************************************************
153 * Perform any BL31 platform setup common to ARM standard platforms
154 ******************************************************************************/
155
bl31_platform_setup(void)156 void bl31_platform_setup(void)
157 {
158 mtk_init_one_level(MTK_INIT_LVL_PLAT_SETUP_0);
159 mtk_init_one_level(MTK_INIT_LVL_PLAT_SETUP_1);
160 }
161
162 /*******************************************************************************
163 * Operations before cold CPU leave BL31.
164 * Switch console to runtime state.
165 ******************************************************************************/
bl31_plat_runtime_setup(void)166 void bl31_plat_runtime_setup(void)
167 {
168 mtk_init_one_level(MTK_INIT_LVL_PLAT_RUNTIME);
169 console_switch_state(CONSOLE_FLAG_RUNTIME);
170 }
171
plat_get_syscnt_freq2(void)172 unsigned int plat_get_syscnt_freq2(void)
173 {
174 return SYS_COUNTER_FREQ_IN_HZ;
175 }
176
