1#
2# Copyright (c) 2019-2021, Broadcom
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# Set the toc_flags to 1 for 100% speed operation
8# Set the toc_flags to 2 for 50% speed operation
9# Set the toc_flags to 3 for 25% speed operation
10# Set the toc_flags bit 3 to indicate ignore the fip in UEFI copy mode
11PLAT_TOC_FLAGS := 0x0
12
13# Set the IHOST_PLL_FREQ to,
14# 1 for full speed
15# 2 for 50% speed
16# 3 for 25% speed
17# 0 for bypass
18$(eval $(call add_define_val,IHOST_PLL_FREQ,1))
19
20# Enable workaround for ERRATA_A72_859971
21ERRATA_A72_859971 := 1
22
23# Cache Coherency Interconnect Driver needed
24DRIVER_CC_ENABLE := 1
25$(eval $(call add_define,DRIVER_CC_ENABLE))
26
27# Enable to erase eMMC
28INCLUDE_EMMC_DRIVER_ERASE_CODE := 0
29
30ifeq (${INCLUDE_EMMC_DRIVER_ERASE_CODE},1)
31$(eval $(call add_define,INCLUDE_EMMC_DRIVER_ERASE_CODE))
32endif
33
34# BL31 is in DRAM
35ARM_BL31_IN_DRAM	:=	1
36
37ifneq (${USE_EMULATOR},yes)
38STINGRAY_EMULATION_SETUP	:=	0
39ifeq (${FASTBOOT_TYPE},)
40override FASTBOOT_TYPE		:=	0
41endif
42USE_PAXB := yes
43USE_PAXC := yes
44USE_CHIMP := yes
45endif
46
47USE_CRMU_SRAM := yes
48
49# Disable FS4 clocks - they can be reenabled when needed by linux
50FS4_DISABLE_CLOCK := yes
51
52# Enable error logging by default for Stingray
53BCM_ELOG := yes
54
55# Enable FRU support by default for Stingray
56ifeq (${USE_FRU},)
57USE_FRU := no
58endif
59
60# Use single cluster
61ifeq (${USE_SINGLE_CLUSTER},yes)
62$(info Using Single Cluster)
63$(eval $(call add_define,USE_SINGLE_CLUSTER))
64endif
65
66# Use DDR
67ifeq (${USE_DDR},yes)
68$(info Using DDR)
69$(eval $(call add_define,USE_DDR))
70endif
71
72ifeq (${BOARD_CFG},)
73BOARD_CFG := bcm958742t
74endif
75
76# Use USB
77ifeq (${USE_USB},yes)
78$(info Using USB)
79$(eval $(call add_define,USE_USB))
80endif
81
82# Use PAXB
83ifeq (${USE_PAXB},yes)
84$(info Using PAXB)
85$(eval $(call add_define,USE_PAXB))
86endif
87
88# Use FS4
89ifeq (${USE_FS4},yes)
90$(info Using FS4)
91$(eval $(call add_define,USE_FS4))
92endif
93
94# Use FS6
95ifeq (${USE_FS6},yes)
96$(info Using FS6)
97$(eval $(call add_define,USE_FS6))
98endif
99
100# Disable FS4 clock
101ifeq (${FS4_DISABLE_CLOCK},yes)
102$(info Using FS4_DISABLE_CLOCK)
103$(eval $(call add_define,FS4_DISABLE_CLOCK))
104endif
105
106ifneq (${NCSI_IO_DRIVE_STRENGTH_MA},)
107$(info Using NCSI_IO_DRIVE_STRENGTH_MA)
108$(eval $(call add_define,NCSI_IO_DRIVE_STRENGTH_MA))
109endif
110
111# Use NAND
112ifeq (${USE_NAND},$(filter yes, ${USE_NAND}))
113$(info Using NAND)
114$(eval $(call add_define,USE_NAND))
115endif
116
117# Enable Broadcom error logging support
118ifeq (${BCM_ELOG},yes)
119$(info Using BCM_ELOG)
120$(eval $(call add_define,BCM_ELOG))
121endif
122
123# BL31 build for standalone mode
124ifeq (${STANDALONE_BL31},yes)
125RESET_TO_BL31 := 1
126$(info Using RESET_TO_BL31)
127endif
128
129# BL31 force full frequency for all CPUs
130ifeq (${BL31_FORCE_CPU_FULL_FREQ},yes)
131$(info Using BL31_FORCE_CPU_FULL_FREQ)
132$(eval $(call add_define,BL31_FORCE_CPU_FULL_FREQ))
133endif
134
135# Enable non-secure accesses to CCN registers
136ifeq (${BL31_CCN_NONSECURE},yes)
137$(info Using BL31_CCN_NONSECURE)
138$(eval $(call add_define,BL31_CCN_NONSECURE))
139endif
140
141# Use ChiMP
142ifeq (${USE_CHIMP},yes)
143$(info Using ChiMP)
144$(eval $(call add_define,USE_CHIMP))
145endif
146
147# Use PAXC
148ifeq (${USE_PAXC},yes)
149$(info Using PAXC)
150$(eval $(call add_define,USE_PAXC))
151ifeq (${CHIMPFW_USE_SIDELOAD},yes)
152$(info Using ChiMP FW sideload)
153$(eval $(call add_define,CHIMPFW_USE_SIDELOAD))
154endif
155$(eval $(call add_define,FASTBOOT_TYPE))
156$(eval $(call add_define,CHIMP_FB1_ENTRY))
157endif
158
159ifeq (${DEFAULT_SWREG_CONFIG}, 1)
160$(eval $(call add_define,DEFAULT_SWREG_CONFIG))
161endif
162
163ifeq (${CHIMP_ALWAYS_NEEDS_QSPI},yes)
164$(eval $(call add_define,CHIMP_ALWAYS_NEEDS_QSPI))
165endif
166
167# For testing purposes, use memsys stubs.  Remove once memsys is fully tested.
168USE_MEMSYS_STUBS := yes
169
170# Default, use BL1_RW area
171ifneq (${BL2_USE_BL1_RW},no)
172$(eval $(call add_define,USE_BL1_RW))
173endif
174
175# Default soft reset is L3
176$(eval $(call add_define,CONFIG_SOFT_RESET_L3))
177
178# Enable Chip OTP driver
179DRIVER_OCOTP_ENABLE := 1
180
181ifneq (${WARMBOOT_DDR_S3_SUPPORT},)
182DRIVER_SPI_ENABLE := 1
183endif
184
185include plat/brcm/board/common/board_common.mk
186
187SOC_DIR			:= 	brcm/board/stingray
188
189PLAT_INCLUDES		+=	-Iplat/${SOC_DIR}/include/ \
190				-Iinclude/plat/brcm/common/ \
191				-Iplat/brcm/common/
192
193PLAT_BL_COMMON_SOURCES	+=	lib/cpus/aarch64/cortex_a72.S \
194				plat/${SOC_DIR}/aarch64/plat_helpers.S \
195				drivers/ti/uart/aarch64/16550_console.S \
196				plat/${SOC_DIR}/src/tz_sec.c \
197				drivers/arm/tzc/tzc400.c \
198				plat/${SOC_DIR}/driver/plat_emmc.c \
199				plat/${SOC_DIR}/src/topology.c \
200				drivers/brcm/mdio/mdio.c
201
202ifeq (${USE_CHIMP},yes)
203PLAT_BL_COMMON_SOURCES	+=	drivers/brcm/chimp.c
204endif
205
206ifeq (${USE_USB},yes)
207PLAT_BL_COMMON_SOURCES	+=	plat/${SOC_DIR}/driver/usb.c \
208				plat/${SOC_DIR}/driver/usb_phy.c
209endif
210
211BL2_SOURCES		+=	plat/${SOC_DIR}/driver/ihost_pll_config.c \
212				plat/${SOC_DIR}/src/bl2_setup.c \
213				plat/${SOC_DIR}/driver/swreg.c
214
215ifeq (${USE_DDR},yes)
216PLAT_INCLUDES		+=	-Iplat/${SOC_DIR}/driver/ddr/soc/include
217else
218PLAT_INCLUDES		+=	-Iplat/${SOC_DIR}/driver/ext_sram_init
219BL2_SOURCES		+=	plat/${SOC_DIR}/driver/ext_sram_init/ext_sram_init.c
220endif
221
222# Include GICv3 driver files
223include drivers/arm/gic/v3/gicv3.mk
224
225BRCM_GIC_SOURCES	:=	${GICV3_SOURCES}		\
226				plat/common/plat_gicv3.c	\
227				plat/brcm/common/brcm_gicv3.c
228
229BL31_SOURCES		+=	\
230				drivers/arm/ccn/ccn.c \
231				plat/brcm/board/common/timer_sync.c \
232				plat/brcm/common/brcm_ccn.c \
233				plat/common/plat_psci_common.c \
234				plat/${SOC_DIR}/driver/ihost_pll_config.c \
235				plat/${SOC_DIR}/src/bl31_setup.c \
236				plat/${SOC_DIR}/src/fsx.c \
237				plat/${SOC_DIR}/src/iommu.c \
238				plat/${SOC_DIR}/src/sdio.c \
239				${BRCM_GIC_SOURCES}
240
241ifneq (${NCSI_IO_DRIVE_STRENGTH_MA},)
242BL31_SOURCES   +=      plat/${SOC_DIR}/src/ncsi.c
243endif
244
245ifeq (${USE_PAXB},yes)
246BL31_SOURCES   +=      plat/${SOC_DIR}/src/paxb.c
247BL31_SOURCES   +=      plat/${SOC_DIR}/src/sr_paxb_phy.c
248endif
249
250ifeq (${USE_PAXC},yes)
251BL31_SOURCES   +=      plat/${SOC_DIR}/src/paxc.c
252endif
253
254ifdef SCP_BL2
255PLAT_INCLUDES		+=	-Iplat/brcm/common/
256
257BL2_SOURCES		+=	plat/brcm/common/brcm_mhu.c \
258				plat/brcm/common/brcm_scpi.c \
259				plat/${SOC_DIR}/src/scp_utils.c \
260				plat/${SOC_DIR}/src/scp_cmd.c \
261				drivers/brcm/scp.c
262
263BL31_SOURCES		+=	plat/brcm/common/brcm_mhu.c \
264				plat/brcm/common/brcm_scpi.c \
265				plat/${SOC_DIR}/src/brcm_pm_ops.c
266else
267BL31_SOURCES		+=	plat/${SOC_DIR}/src/ihost_pm.c \
268				plat/${SOC_DIR}/src/pm.c
269endif
270
271ifeq (${ELOG_SUPPORT},1)
272ifeq (${ELOG_STORE_MEDIA},DDR)
273BL2_SOURCES		+=	plat/brcm/board/common/bcm_elog_ddr.c
274endif
275endif
276
277ifeq (${BL31_BOOT_PRELOADED_SCP}, 1)
278ifdef SCP_BL2
279SCP_CFG_DIR=$(dir ${SCP_BL2})
280PLAT_INCLUDES	+=	-I${SCP_CFG_DIR}
281endif
282PLAT_INCLUDES	+=	-Iplat/brcm/common/
283
284# By default use OPTEE Assigned memory
285PRELOADED_SCP_BASE ?= 0x8E000000
286PRELOADED_SCP_SIZE ?= 0x10000
287$(eval $(call add_define,PRELOADED_SCP_BASE))
288$(eval $(call add_define,PRELOADED_SCP_SIZE))
289$(eval $(call add_define,BL31_BOOT_PRELOADED_SCP))
290BL31_SOURCES += plat/${SOC_DIR}/src/scp_utils.c \
291		plat/${SOC_DIR}/src/scp_cmd.c \
292		drivers/brcm/scp.c
293endif
294
295# Do not execute the startup code on warm reset.
296PROGRAMMABLE_RESET_ADDRESS	:=	1
297
298# Nitro FW, config and Crash log uses secure DDR memory
299# Inaddition to above, Nitro master and slave is also secure
300ifneq ($(NITRO_SECURE_ACCESS),)
301$(eval $(call add_define,NITRO_SECURE_ACCESS))
302$(eval $(call add_define,DDR_NITRO_SECURE_REGION_START))
303$(eval $(call add_define,DDR_NITRO_SECURE_REGION_END))
304endif
305