1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SGI_SOC_CSS_DEF_V2_H 8 #define SGI_SOC_CSS_DEF_V2_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* 14 * Definitions common to all ARM CSS SoCs 15 */ 16 17 /* Following covers ARM CSS SoC Peripherals */ 18 19 #define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000) 20 #define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000) 21 22 #define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000) 23 #define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000) 24 25 #define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000) 26 27 /* Memory controller */ 28 #define SOC_MEMCNTRL_BASE UL(0x10000000) 29 #define SOC_MEMCNTRL_SIZE UL(0x10000000) 30 31 /* SoC NIC-400 Global Programmers View (GPV) */ 32 #define SOC_CSS_NIC400_BASE UL(0x0ED00000) 33 34 #define SOC_CSS_NIC400_USB_EHCI U(0) 35 #define SOC_CSS_NIC400_TLX_MASTER U(1) 36 #define SOC_CSS_NIC400_USB_OHCI U(2) 37 #define SOC_CSS_NIC400_PL354_SMC U(3) 38 /* 39 * The apb4_bridge controls access to: 40 * - the PCIe configuration registers 41 * - the MMU units for USB, HDLCD and DMA 42 */ 43 #define SOC_CSS_NIC400_APB4_BRIDGE U(4) 44 45 /* Non-volatile counters */ 46 #define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000) 47 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) 48 #define TFW_NVCTR_SIZE U(4) 49 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 50 #define NTFW_CTR_SIZE U(4) 51 52 /* Keys */ 53 #define SOC_KEYS_BASE UL(0x0EE80000) 54 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 55 #define TZ_PUB_KEY_HASH_SIZE U(32) 56 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 57 #define HU_KEY_SIZE U(16) 58 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 59 #define END_KEY_SIZE U(32) 60 61 #define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ 62 SOC_PLATFORM_PERIPH_BASE, \ 63 SOC_PLATFORM_PERIPH_SIZE, \ 64 MT_DEVICE | MT_RW | MT_SECURE) 65 66 #if SPM_MM 67 /* 68 * Memory map definition for the platform peripheral memory region that is 69 * accessible from S-EL0 (with secure user mode access). 70 */ 71 #define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \ 72 MAP_REGION_FLAT( \ 73 SOC_PLATFORM_PERIPH_BASE, \ 74 SOC_PLATFORM_PERIPH_SIZE, \ 75 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 76 #endif 77 78 #define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ 79 SOC_SYSTEM_PERIPH_BASE, \ 80 SOC_SYSTEM_PERIPH_SIZE, \ 81 MT_DEVICE | MT_RW | MT_SECURE) 82 83 #define SOC_MEMCNTRL_MAP_DEVICE MAP_REGION_FLAT( \ 84 SOC_MEMCNTRL_BASE, \ 85 SOC_MEMCNTRL_SIZE, \ 86 MT_DEVICE | MT_RW | MT_SECURE) 87 88 #define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n) \ 89 MAP_REGION_FLAT( \ 90 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE, \ 91 SOC_MEMCNTRL_SIZE, \ 92 MT_DEVICE | MT_RW | MT_SECURE) 93 94 /* 95 * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. 96 */ 97 #define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5) 98 #define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12) 99 100 /* 101 * Required platform porting definitions common to all ARM CSS SoCs 102 */ 103 /* 2MB used for SCP DDR retraining */ 104 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000) 105 106 /* V2M motherboard system registers & offsets */ 107 #define V2M_SYSREGS_BASE UL(0x0C010000) 108 #define V2M_SYS_LED U(0x8) 109 110 /* 111 * V2M sysled bit definitions. The values written to this 112 * register are defined in arch.h & runtime_svc.h. Only 113 * used by the primary cpu to diagnose any cold boot issues. 114 * 115 * SYS_LED[0] - Security state (S=0/NS=1) 116 * SYS_LED[2:1] - Exception Level (EL3-EL0) 117 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 118 * 119 */ 120 #define V2M_SYS_LED_SS_SHIFT U(0) 121 #define V2M_SYS_LED_EL_SHIFT U(1) 122 #define V2M_SYS_LED_EC_SHIFT U(3) 123 124 #define V2M_SYS_LED_SS_MASK U(0x01) 125 #define V2M_SYS_LED_EL_MASK U(0x03) 126 #define V2M_SYS_LED_EC_MASK U(0x1f) 127 128 /* NOR Flash */ 129 #define V2M_FLASH0_BASE UL(0x08000000) 130 #define V2M_FLASH0_SIZE UL(0x04000000) 131 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 132 133 /* 134 * The flash can be mapped either as read-only or read-write. 135 * 136 * If it is read-write then it should also be mapped as device memory because 137 * NOR flash programming involves sending a fixed, ordered sequence of commands. 138 * 139 * If it is read-only then it should also be mapped as: 140 * - Normal memory, because reading from NOR flash is transparent, it is like 141 * reading from RAM. 142 * - Non-executable by default. If some parts of the flash need to be executable 143 * then platform code is responsible for re-mapping the appropriate portion 144 * of it as executable. 145 */ 146 #define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 147 V2M_FLASH0_SIZE, \ 148 MT_DEVICE | MT_RW | MT_SECURE) 149 150 #define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 151 V2M_FLASH0_SIZE, \ 152 MT_RO_DATA | MT_SECURE) 153 154 #define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 155 V2M_FLASH0_SIZE, \ 156 MT_DEVICE | MT_RO | MT_SECURE) 157 158 /* Platform ID address */ 159 #define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0) 160 161 /* Platform ID related accessors */ 162 #define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F) 163 #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00) 164 #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00) 165 #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08) 166 #define BOARD_CSS_PLAT_TYPE_RTL U(0x00) 167 #define BOARD_CSS_PLAT_TYPE_FPGA U(0x01) 168 #define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02) 169 #define BOARD_CSS_PLAT_TYPE_FVP U(0x03) 170 171 #ifndef __ASSEMBLER__ 172 173 #include <lib/mmio.h> 174 175 #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 176 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 177 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 178 179 #endif /* __ASSEMBLER__ */ 180 181 182 #define MAX_IO_DEVICES U(3) 183 #define MAX_IO_HANDLES U(4) 184 185 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 186 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 187 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 188 189 #if ARM_GPT_SUPPORT 190 /* 191 * Offset of the FIP in the GPT image. BL1 component uses this option 192 * as it does not load the partition table to get the FIP base 193 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 194 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 195 */ 196 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 197 #endif /* ARM_GPT_SUPPORT */ 198 199 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 200 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 201 202 #endif /* SGI_SOC_CSS_DEF_V2_H */ 203
