1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 28# progbits limit. We need a way to build all useful configurations while waiting 29# on the fvp to increase its SRAM size. The problem is twofild: 30# 1. the cleanup that introduced these enables cleaned up tf-a a little too 31# well and things that previously (incorrectly) were enabled, no longer are. 32# A bunch of CI configs build subtly incorrectly and this combo makes it 33# necessary to forcefully and unconditionally enable them here. 34# 2. the progbits limit is exceeded only when the tsp is involved. However, 35# there are tsp CI configs that run on very high architecture revisions so 36# disabling everything isn't an option. 37# The fix is to enable everything, as before. When the tsp is included, though, 38# we need to slim the size down. In that case, disable all optional features, 39# that will not be present in CI when the tsp is. 40# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 41# for it. 42# TODO: make all of this unconditional (or only base the condition on 43# ARM_ARCH_* when the makefile supports it). 44ifneq (${DRTM_SUPPORT}, 1) 45ifneq (${SPD}, tspd) 46 ENABLE_FEAT_AMU := 2 47 ENABLE_FEAT_AMUv1p1 := 2 48 ENABLE_FEAT_HCX := 2 49 ENABLE_MPAM_FOR_LOWER_ELS := 2 50 ENABLE_FEAT_RNG := 2 51 ENABLE_FEAT_TWED := 2 52 ENABLE_FEAT_GCS := 2 53 ENABLE_FEAT_RAS := 2 54ifeq (${ARCH}, aarch64) 55ifneq (${SPD}, spmd) 56ifeq (${SPM_MM}, 0) 57ifeq (${ENABLE_RME}, 0) 58ifeq (${CTX_INCLUDE_FPREGS}, 0) 59 ENABLE_SME_FOR_NS := 2 60 ENABLE_SME2_FOR_NS := 2 61endif 62endif 63endif 64endif 65endif 66endif 67 68# enable unconditionally for all builds 69ifeq (${ARCH}, aarch64) 70ifeq (${ENABLE_RME},0) 71 ENABLE_BRBE_FOR_NS := 2 72endif 73endif 74ENABLE_TRBE_FOR_NS := 2 75ENABLE_SYS_REG_TRACE_FOR_NS := 2 76ENABLE_FEAT_CSV2_2 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_VHE := 2 80CTX_INCLUDE_NEVE_REGS := 2 81ENABLE_FEAT_SEL2 := 2 82ENABLE_TRF_FOR_NS := 2 83ENABLE_FEAT_ECV := 2 84ENABLE_FEAT_FGT := 2 85ENABLE_FEAT_TCR2 := 2 86ENABLE_FEAT_S2PIE := 2 87ENABLE_FEAT_S1PIE := 2 88ENABLE_FEAT_S2POE := 2 89ENABLE_FEAT_S1POE := 2 90endif 91 92# The FVP platform depends on this macro to build with correct GIC driver. 93$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 94 95# Pass FVP_CLUSTER_COUNT to the build system. 96$(eval $(call add_define,FVP_CLUSTER_COUNT)) 97 98# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 99$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 100 101# Pass FVP_MAX_PE_PER_CPU to the build system. 102$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 103 104# Pass FVP_GICR_REGION_PROTECTION to the build system. 105$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 106 107# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 108# choose the CCI driver , else the CCN driver 109ifeq ($(FVP_CLUSTER_COUNT), 0) 110$(error "Incorrect cluster count specified for FVP port") 111else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 112FVP_INTERCONNECT_DRIVER := FVP_CCI 113else 114FVP_INTERCONNECT_DRIVER := FVP_CCN 115endif 116 117$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 118 119# Choose the GIC sources depending upon the how the FVP will be invoked 120ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 121 122# The GIC model (GIC-600 or GIC-500) will be detected at runtime 123GICV3_SUPPORT_GIC600 := 1 124GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 125 126# Include GICv3 driver files 127include drivers/arm/gic/v3/gicv3.mk 128 129FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 130 plat/common/plat_gicv3.c \ 131 plat/arm/common/arm_gicv3.c 132 133 ifeq ($(filter 1,${RESET_TO_BL2} \ 134 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 135 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 136 endif 137 138else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 139 140# No GICv4 extension 141GIC_ENABLE_V4_EXTN := 0 142$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 143 144# Include GICv2 driver files 145include drivers/arm/gic/v2/gicv2.mk 146 147FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 148 plat/common/plat_gicv2.c \ 149 plat/arm/common/arm_gicv2.c 150 151FVP_DT_PREFIX := fvp-base-gicv2-psci 152else 153$(error "Incorrect GIC driver chosen on FVP port") 154endif 155 156ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 157FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 158else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 159FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 160 plat/arm/common/arm_ccn.c 161else 162$(error "Incorrect CCN driver chosen on FVP port") 163endif 164 165FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 166 plat/arm/board/fvp/fvp_security.c \ 167 plat/arm/common/arm_tzc400.c 168 169 170PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 171 -Iinclude/lib/psa 172 173 174PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 175 176FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 177 178ifeq (${ARCH}, aarch64) 179 180# select a different set of CPU files, depending on whether we compile for 181# hardware assisted coherency cores or not 182ifeq (${HW_ASSISTED_COHERENCY}, 0) 183# Cores used without DSU 184 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 185 lib/cpus/aarch64/cortex_a53.S \ 186 lib/cpus/aarch64/cortex_a57.S \ 187 lib/cpus/aarch64/cortex_a72.S \ 188 lib/cpus/aarch64/cortex_a73.S 189else 190# Cores used with DSU only 191 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 192 # AArch64-only cores 193 # TODO: add all cores to the appropriate lists 194 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 195 lib/cpus/aarch64/cortex_a65ae.S \ 196 lib/cpus/aarch64/cortex_a76.S \ 197 lib/cpus/aarch64/cortex_a76ae.S \ 198 lib/cpus/aarch64/cortex_a77.S \ 199 lib/cpus/aarch64/cortex_a78.S \ 200 lib/cpus/aarch64/cortex_a78c.S \ 201 lib/cpus/aarch64/cortex_a710.S \ 202 lib/cpus/aarch64/neoverse_n_common.S \ 203 lib/cpus/aarch64/neoverse_n1.S \ 204 lib/cpus/aarch64/neoverse_n2.S \ 205 lib/cpus/aarch64/neoverse_v1.S \ 206 lib/cpus/aarch64/neoverse_e1.S \ 207 lib/cpus/aarch64/cortex_x2.S 208 endif 209 # AArch64/AArch32 cores 210 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 211 lib/cpus/aarch64/cortex_a75.S 212endif 213 214else 215FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 216 lib/cpus/aarch32/cortex_a57.S 217endif 218 219BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 220 drivers/arm/sp805/sp805.c \ 221 drivers/delay_timer/delay_timer.c \ 222 drivers/io/io_semihosting.c \ 223 lib/semihosting/semihosting.c \ 224 lib/semihosting/${ARCH}/semihosting_call.S \ 225 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 226 plat/arm/board/fvp/fvp_bl1_setup.c \ 227 plat/arm/board/fvp/fvp_err.c \ 228 plat/arm/board/fvp/fvp_io_storage.c \ 229 ${FVP_CPU_LIBS} \ 230 ${FVP_INTERCONNECT_SOURCES} 231 232ifeq (${USE_SP804_TIMER},1) 233BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 234else 235BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 236endif 237 238 239BL2_SOURCES += drivers/arm/sp805/sp805.c \ 240 drivers/io/io_semihosting.c \ 241 lib/utils/mem_region.c \ 242 lib/semihosting/semihosting.c \ 243 lib/semihosting/${ARCH}/semihosting_call.S \ 244 plat/arm/board/fvp/fvp_bl2_setup.c \ 245 plat/arm/board/fvp/fvp_err.c \ 246 plat/arm/board/fvp/fvp_io_storage.c \ 247 plat/arm/common/arm_nor_psci_mem_protect.c \ 248 ${FVP_SECURITY_SOURCES} 249 250 251ifeq (${COT_DESC_IN_DTB},1) 252BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 253endif 254 255ifeq (${ENABLE_RME},1) 256BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 257 258BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 259 plat/arm/board/fvp/fvp_realm_attest_key.c 260 261# FVP platform does not support RSS, but it can leverage RSS APIs to 262# provide hardcoded token/key on request. 263BL31_SOURCES += lib/psa/delegated_attestation.c 264 265endif 266 267ifeq (${ENABLE_FEAT_RNG_TRAP},1) 268BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 269endif 270 271ifeq (${RESET_TO_BL2},1) 272BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 273 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 274 ${FVP_CPU_LIBS} \ 275 ${FVP_INTERCONNECT_SOURCES} 276endif 277 278ifeq (${USE_SP804_TIMER},1) 279BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 280endif 281 282BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 283 ${FVP_SECURITY_SOURCES} 284 285ifeq (${USE_SP804_TIMER},1) 286BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 287endif 288 289BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 290 drivers/arm/smmu/smmu_v3.c \ 291 drivers/delay_timer/delay_timer.c \ 292 drivers/cfi/v2m/v2m_flash.c \ 293 lib/utils/mem_region.c \ 294 plat/arm/board/fvp/fvp_bl31_setup.c \ 295 plat/arm/board/fvp/fvp_console.c \ 296 plat/arm/board/fvp/fvp_pm.c \ 297 plat/arm/board/fvp/fvp_topology.c \ 298 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 299 plat/arm/common/arm_nor_psci_mem_protect.c \ 300 ${FVP_CPU_LIBS} \ 301 ${FVP_GIC_SOURCES} \ 302 ${FVP_INTERCONNECT_SOURCES} \ 303 ${FVP_SECURITY_SOURCES} 304 305# Support for fconf in BL31 306# Added separately from the above list for better readability 307ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 308BL31_SOURCES += lib/fconf/fconf.c \ 309 lib/fconf/fconf_dyn_cfg_getter.c \ 310 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 311 312BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 313 314ifeq (${SEC_INT_DESC_IN_FCONF},1) 315BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 316endif 317 318endif 319 320ifeq (${USE_SP804_TIMER},1) 321BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 322else 323BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 324endif 325 326# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 327ifdef UNIX_MK 328FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 329FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 330 ${PLAT}_fw_config.dts \ 331 ${PLAT}_tb_fw_config.dts \ 332 ${PLAT}_soc_fw_config.dts \ 333 ${PLAT}_nt_fw_config.dts \ 334 ) 335 336FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 337FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 338FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 339FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 340 341ifeq (${SPD},tspd) 342FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 343FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 344 345# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 346$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 347endif 348 349ifeq (${SPD},spmd) 350 351ifeq ($(ARM_SPMC_MANIFEST_DTS),) 352ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 353endif 354 355FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 356FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 357 358# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 359$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 360endif 361 362# Add the FW_CONFIG to FIP and specify the same to certtool 363$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 364# Add the TB_FW_CONFIG to FIP and specify the same to certtool 365$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 366# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 367$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 368# Add the NT_FW_CONFIG to FIP and specify the same to certtool 369$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 370 371FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 372$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 373 374# Add the HW_CONFIG to FIP and specify the same to certtool 375$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 376endif 377 378# Enable dynamic mitigation support by default 379DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 380 381ifneq (${ENABLE_FEAT_AMU},0) 382BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 383 lib/cpus/aarch64/cpuamu_helpers.S 384 385ifeq (${HW_ASSISTED_COHERENCY}, 1) 386BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 387 lib/cpus/aarch64/neoverse_n1_pubsub.c 388endif 389endif 390 391ifeq (${RAS_FFH_SUPPORT},1) 392BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 393endif 394 395ifneq (${ENABLE_STACK_PROTECTOR},0) 396PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 397endif 398 399ifeq (${ARCH},aarch32) 400 NEED_BL32 := yes 401endif 402 403# Enable the dynamic translation tables library. 404ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 405 ifeq (${ARCH},aarch32) 406 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 407 else # AArch64 408 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 409 endif 410endif 411 412ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 413 ifeq (${ARCH},aarch32) 414 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 415 else # AArch64 416 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 417 ifeq (${SPD},tspd) 418 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 419 endif 420 endif 421endif 422 423ifeq (${USE_DEBUGFS},1) 424 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 425endif 426 427# Add support for platform supplied linker script for BL31 build 428$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 429 430ifneq (${RESET_TO_BL2}, 0) 431 override BL1_SOURCES = 432endif 433 434# RSS is not supported on FVP right now. Thus, we use the mocked version 435# of the provided PSA APIs. They return with success and hard-coded token/key. 436PLAT_RSS_NOT_SUPPORTED := 1 437 438# Include Measured Boot makefile before any Crypto library makefile. 439# Crypto library makefile may need default definitions of Measured Boot build 440# flags present in Measured Boot makefile. 441ifeq (${MEASURED_BOOT},1) 442 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 443 $(info Including ${RSS_MEASURED_BOOT_MK}) 444 include ${RSS_MEASURED_BOOT_MK} 445 446 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 447 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 448 endif 449 450 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 451 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 452endif 453 454include plat/arm/board/common/board_common.mk 455include plat/arm/common/arm_common.mk 456 457ifeq (${MEASURED_BOOT},1) 458BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 459 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 460 lib/psa/measured_boot.c 461 462BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 463 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 464 lib/psa/measured_boot.c 465 466# Even though RSS is not supported on FVP (see above), we support overriding 467# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 468# the code to detect any build regressions. The resulting firmware will not be 469# functional. 470ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 471 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 472 include drivers/arm/rss/rss_comms.mk 473 BL1_SOURCES += ${RSS_COMMS_SOURCES} 474 BL2_SOURCES += ${RSS_COMMS_SOURCES} 475 BL31_SOURCES += ${RSS_COMMS_SOURCES} 476 477 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 478 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 479 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 480endif 481 482endif 483 484ifeq (${DRTM_SUPPORT}, 1) 485BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 486 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 487 plat/arm/board/fvp/fvp_drtm_err.c \ 488 plat/arm/board/fvp/fvp_drtm_measurement.c \ 489 plat/arm/board/fvp/fvp_drtm_stub.c \ 490 plat/arm/common/arm_dyn_cfg.c \ 491 plat/arm/board/fvp/fvp_err.c 492endif 493 494ifeq (${TRUSTED_BOARD_BOOT}, 1) 495BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 496BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 497 498# FVP being a development platform, enable capability to disable Authentication 499# dynamically if TRUSTED_BOARD_BOOT is set. 500DYN_DISABLE_AUTH := 1 501endif 502 503ifeq (${SPMC_AT_EL3}, 1) 504PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 505endif 506 507PSCI_OS_INIT_MODE := 1 508 509ifeq (${SPD},spmd) 510BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 511endif 512 513# Test specific macros, keep them at bottom of this file 514$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 515ifeq (${PLATFORM_TEST_EA_FFH}, 1) 516 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 517 $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 518 endif 519BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 520endif 521 522$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 523ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 524 ifeq (${RAS_EXTENSION}, 0) 525 $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") 526 endif 527endif 528 529ifeq (${ERRATA_ABI_SUPPORT}, 1) 530include plat/arm/board/fvp/fvp_cpu_errata.mk 531endif 532
