1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_PAS_DEF_H 7 #define ARM_PAS_DEF_H 8 9 #include <lib/gpt_rme/gpt_rme.h> 10 #include <plat/arm/common/arm_def.h> 11 12 /***************************************************************************** 13 * PAS regions used to initialize the Granule Protection Table (GPT) 14 ****************************************************************************/ 15 16 /* 17 * The PA space is initially mapped in the GPT as follows: 18 * 19 * ============================================================================ 20 * Base Addr| Size |L? GPT|PAS |Content |Comment 21 * ============================================================================ 22 * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping 23 * | | | |TSRAM (EL3 data) | 24 * 00000000 | | | |IO (incl.UARTs & GIC) | 25 * ---------------------------------------------------------------------------- 26 * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping 27 * 40000000 | | | | | 28 * ---------------------------------------------------------------------------- 29 * 2GB |2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip 30 * 80000000 | | | | | 31 * ---------------------------------------------------------------------------- 32 * 4GB-64MB |64MB-32MB-4MB|L1 GPT|SECURE|DRAM TZC |Use T.Descrip 33 * FC000000 | | | | | 34 * ---------------------------------------------------------------------------- 35 * 4GB-32MB | | | | | 36 * -3MB-1MB |32MB |L1 GPT|REALM |RMM |Use T.Descrip 37 * FDC00000 | | | | | 38 * ---------------------------------------------------------------------------- 39 * 4GB-3MB | | | | | 40 * -1MB |3MB |L1 GPT|ROOT |EL3 DRAM data |Use T.Descrip 41 * FFC00000 | | | | | 42 * ---------------------------------------------------------------------------- 43 * 4GB-1MB |1MB |L1 GPT|ROOT |DRAM (L1 GPTs, SCP TZC) |Fixed mapping 44 * FFF00000 | | | | | 45 * ---------------------------------------------------------------------------- 46 * 34GB |2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip 47 * 880000000| | | | | 48 * ============================================================================ 49 * 50 * - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section. 51 * - ~1MB of L1 GPTs reside at the top of DRAM1 (TZC area). 52 * - The first 1GB region has GPT_GPI_ANY and, therefore, is not protected by 53 * the GPT. 54 * - The DRAM TZC area is split into three regions: the L1 GPT region and 55 * 3MB of region below that are defined as GPT_GPI_ROOT, 32MB Realm region 56 * below that is defined as GPT_GPI_REALM and the rest of it is defined as 57 * GPT_GPI_SECURE. 58 */ 59 60 /* TODO: This might not be the best way to map the PAS */ 61 62 /* Device memory 0 to 2GB */ 63 #define ARM_PAS_1_BASE (U(0)) 64 #define ARM_PAS_1_SIZE ((ULL(1) << 31)) /* 2GB */ 65 66 /* NS memory 2GB to (end - 64MB) */ 67 #define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE) 68 #define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE) 69 70 /* Shared area between EL3 and RMM */ 71 #define ARM_PAS_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 72 #define ARM_PAS_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 73 74 /* Secure TZC region */ 75 #define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE) 76 #define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE) 77 78 /* NS memory 2GB */ 79 #define ARM_PAS_4_BASE ARM_DRAM2_BASE 80 #define ARM_PAS_4_SIZE ((ULL(1) << 31)) /* 2GB */ 81 82 #define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \ 83 ARM_PAS_1_SIZE, \ 84 GPT_GPI_ANY) 85 86 #define ARM_PAS_KERNEL GPT_MAP_REGION_GRANULE(ARM_PAS_2_BASE, \ 87 ARM_PAS_2_SIZE, \ 88 GPT_GPI_NS) 89 90 #define ARM_PAS_SECURE GPT_MAP_REGION_GRANULE(ARM_PAS_3_BASE, \ 91 ARM_PAS_3_SIZE, \ 92 GPT_GPI_SECURE) 93 94 #define ARM_PAS_KERNEL_1 GPT_MAP_REGION_GRANULE(ARM_PAS_4_BASE, \ 95 ARM_PAS_4_SIZE, \ 96 GPT_GPI_NS) 97 /* 98 * REALM and Shared area share the same PAS, so consider them a single 99 * PAS region to configure in GPT. 100 */ 101 #define ARM_PAS_REALM GPT_MAP_REGION_GRANULE(ARM_REALM_BASE, \ 102 (ARM_PAS_SHARED_SIZE + \ 103 ARM_REALM_SIZE), \ 104 GPT_GPI_REALM) 105 106 #define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ 107 ARM_EL3_TZC_DRAM1_SIZE, \ 108 GPT_GPI_ROOT) 109 110 #define ARM_PAS_GPTS GPT_MAP_REGION_GRANULE(ARM_L1_GPT_ADDR_BASE, \ 111 ARM_L1_GPT_SIZE, \ 112 GPT_GPI_ROOT) 113 114 /* GPT Configuration options */ 115 #define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS 116 117 #endif /* ARM_PAS_DEF_H */ 118
