1/*
2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
10	compatible = "arm,tc";
11	interrupt-parent = <&gic>;
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	aliases {
16		serial0 = &soc_uart0;
17	};
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		cpu-map {
28			cluster0 {
29				core0 {
30					cpu = <&CPU0>;
31				};
32				core1 {
33					cpu = <&CPU1>;
34				};
35				core2 {
36					cpu = <&CPU2>;
37				};
38				core3 {
39					cpu = <&CPU3>;
40				};
41				core4 {
42					cpu = <&CPU4>;
43				};
44				core5 {
45					cpu = <&CPU5>;
46				};
47				core6 {
48					cpu = <&CPU6>;
49				};
50				core7 {
51					cpu = <&CPU7>;
52				};
53			};
54		};
55
56		/*
57		 * The timings below are just to demonstrate working cpuidle.
58		 * These values may be inaccurate.
59		 */
60		idle-states {
61			entry-method = "arm,psci";
62
63			CPU_SLEEP_0: cpu-sleep-0 {
64				compatible = "arm,idle-state";
65				arm,psci-suspend-param = <0x0010000>;
66				local-timer-stop;
67				entry-latency-us = <300>;
68				exit-latency-us = <1200>;
69				min-residency-us = <2000>;
70			};
71			CLUSTER_SLEEP_0: cluster-sleep-0 {
72				compatible = "arm,idle-state";
73				arm,psci-suspend-param = <0x1010000>;
74				local-timer-stop;
75				entry-latency-us = <400>;
76				exit-latency-us = <1200>;
77				min-residency-us = <2500>;
78			};
79		};
80
81		amus {
82			amu: amu-0 {
83				#address-cells = <1>;
84				#size-cells = <0>;
85
86				mpmm_gear0: counter@0 {
87					reg = <0>;
88
89					enable-at-el3;
90				};
91
92				mpmm_gear1: counter@1 {
93					reg = <1>;
94
95					enable-at-el3;
96				};
97
98				mpmm_gear2: counter@2 {
99					reg = <2>;
100
101					enable-at-el3;
102				};
103			};
104		};
105
106		CPU0:cpu@0 {
107			device_type = "cpu";
108			compatible = "arm,armv8";
109			reg = <0x0>;
110			enable-method = "psci";
111			clocks = <&scmi_dvfs 0>;
112			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
113			capacity-dmips-mhz = <406>;
114			amu = <&amu>;
115			supports-mpmm;
116		};
117
118		CPU1:cpu@100 {
119			device_type = "cpu";
120			compatible = "arm,armv8";
121			reg = <0x100>;
122			enable-method = "psci";
123			clocks = <&scmi_dvfs 0>;
124			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
125			capacity-dmips-mhz = <406>;
126			amu = <&amu>;
127			supports-mpmm;
128		};
129
130		CPU2:cpu@200 {
131			device_type = "cpu";
132			compatible = "arm,armv8";
133			reg = <0x200>;
134			enable-method = "psci";
135			clocks = <&scmi_dvfs 0>;
136			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137			capacity-dmips-mhz = <406>;
138			amu = <&amu>;
139			supports-mpmm;
140		};
141
142		CPU3:cpu@300 {
143			device_type = "cpu";
144			compatible = "arm,armv8";
145			reg = <0x300>;
146			enable-method = "psci";
147			clocks = <&scmi_dvfs 0>;
148			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
149			capacity-dmips-mhz = <406>;
150			amu = <&amu>;
151			supports-mpmm;
152		};
153
154		CPU4:cpu@400 {
155			device_type = "cpu";
156			compatible = "arm,armv8";
157			reg = <0x400>;
158			enable-method = "psci";
159			clocks = <&scmi_dvfs 1>;
160			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
161			capacity-dmips-mhz = <912>;
162			amu = <&amu>;
163			supports-mpmm;
164		};
165
166		CPU5:cpu@500 {
167			device_type = "cpu";
168			compatible = "arm,armv8";
169			reg = <0x500>;
170			enable-method = "psci";
171			clocks = <&scmi_dvfs 1>;
172			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
173			capacity-dmips-mhz = <912>;
174			amu = <&amu>;
175			supports-mpmm;
176		};
177
178		CPU6:cpu@600 {
179			device_type = "cpu";
180			compatible = "arm,armv8";
181			reg = <0x600>;
182			enable-method = "psci";
183			clocks = <&scmi_dvfs 1>;
184			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
185			capacity-dmips-mhz = <912>;
186			amu = <&amu>;
187			supports-mpmm;
188		};
189
190		CPU7:cpu@700 {
191			device_type = "cpu";
192			compatible = "arm,armv8";
193			reg = <0x700>;
194			enable-method = "psci";
195			clocks = <&scmi_dvfs 2>;
196			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
197			capacity-dmips-mhz = <1024>;
198			amu = <&amu>;
199			supports-mpmm;
200		};
201
202	};
203
204	reserved-memory {
205		#address-cells = <2>;
206		#size-cells = <2>;
207		ranges;
208
209		linux,cma {
210			compatible = "shared-dma-pool";
211			reusable;
212			size = <0x0 0x8000000>;
213			linux,cma-default;
214		};
215
216		optee@0xf8e00000 {
217			compatible = "restricted-dma-pool";
218			reg = <0x00000000 0xf8e00000 0 0x00200000>;
219		};
220	};
221
222	psci {
223		compatible = "arm,psci-1.0", "arm,psci-0.2";
224		method = "smc";
225	};
226
227	sram: sram@6000000 {
228		compatible = "mmio-sram";
229		reg = <0x0 0x06000000 0x0 0x8000>;
230
231		#address-cells = <1>;
232		#size-cells = <1>;
233		ranges = <0 0x0 0x06000000 0x8000>;
234
235		cpu_scp_scmi_mem: scp-shmem@0 {
236			compatible = "arm,scmi-shmem";
237			reg = <0x0 0x80>;
238		};
239	};
240
241	mbox_db_rx: mhu@45010000 {
242		compatible = "arm,mhuv2-rx","arm,primecell";
243		reg = <0x0 0x45010000 0x0 0x1000>;
244		clocks = <&soc_refclk100mhz>;
245		clock-names = "apb_pclk";
246		#mbox-cells = <2>;
247		interrupts = <0 317 4>;
248		interrupt-names = "mhu_rx";
249		mhu-protocol = "doorbell";
250		arm,mhuv2-protocols = <0 1>;
251	};
252
253	mbox_db_tx: mhu@45000000 {
254		compatible = "arm,mhuv2-tx","arm,primecell";
255		reg = <0x0 0x45000000 0x0 0x1000>;
256		clocks = <&soc_refclk100mhz>;
257		clock-names = "apb_pclk";
258		#mbox-cells = <2>;
259		interrupt-names = "mhu_tx";
260		mhu-protocol = "doorbell";
261		arm,mhuv2-protocols = <0 1>;
262	};
263
264	cmn-pmu {
265		compatible = "arm,ci-700";
266		reg = <0x0 0x50000000 0x0 0x10000000>;
267		interrupts = <0x0 460 0x4>;
268	};
269
270	scmi {
271		compatible = "arm,scmi";
272		mbox-names = "tx", "rx";
273		mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
274		shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
275		#address-cells = <1>;
276		#size-cells = <0>;
277
278		scmi_dvfs: protocol@13 {
279			reg = <0x13>;
280			#clock-cells = <1>;
281		};
282
283		scmi_clk: protocol@14 {
284			reg = <0x14>;
285			#clock-cells = <1>;
286		};
287	};
288
289	gic: interrupt-controller@2c010000 {
290		compatible = "arm,gic-600", "arm,gic-v3";
291		#address-cells = <2>;
292		#interrupt-cells = <3>;
293		#size-cells = <2>;
294		ranges;
295		interrupt-controller;
296		reg = <0x0 0x30000000 0 0x10000>, /* GICD */
297		      <0x0 0x30080000 0 0x200000>; /* GICR */
298		interrupts = <0x1 0x9 0x4>;
299	};
300
301	timer {
302		compatible = "arm,armv8-timer";
303		interrupts = <0x1 13 0x8>,
304			     <0x1 14 0x8>,
305			     <0x1 11 0x8>,
306			     <0x1 10 0x8>;
307	};
308
309	soc_refclk100mhz: refclk100mhz {
310		compatible = "fixed-clock";
311		#clock-cells = <0>;
312		clock-frequency = <100000000>;
313		clock-output-names = "apb_pclk";
314	};
315
316	soc_refclk60mhz: refclk60mhz {
317		compatible = "fixed-clock";
318		#clock-cells = <0>;
319		clock-frequency = <60000000>;
320		clock-output-names = "iofpga_clk";
321	};
322
323	soc_uartclk:  uartclk {
324		compatible = "fixed-clock";
325		#clock-cells = <0>;
326		clock-frequency = <50000000>;
327		clock-output-names = "uartclk";
328	};
329
330	soc_uart0: uart@7ff80000 {
331		compatible = "arm,pl011", "arm,primecell";
332		reg = <0x0 0x7ff80000 0x0 0x1000>;
333		interrupts = <0x0 116 0x4>;
334		clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
335		clock-names = "uartclk", "apb_pclk";
336		status = "okay";
337	};
338
339	rtc0: rtc@1C170000 {
340		compatible = "arm,pl031", "arm,primecell";
341		reg = <0x0 0x1C170000 0x0 0x1000>;
342		interrupts = <0x0 100 0x4>;
343		clocks = <&soc_refclk100mhz>;
344		clock-names = "apb_pclk";
345		wakeup-source;
346	};
347
348	vencoder {
349		compatible = "drm,virtual-encoder";
350
351		port {
352			vencoder_in: endpoint {
353				remote-endpoint = <&dp_pl0_out0>;
354			};
355		};
356
357		display-timings {
358			panel-timing {
359				clock-frequency = <25175000>;
360				hactive = <640>;
361				vactive = <480>;
362				hfront-porch = <16>;
363				hback-porch = <48>;
364				hsync-len = <96>;
365				vfront-porch = <10>;
366				vback-porch = <33>;
367				vsync-len = <2>;
368			};
369		};
370
371	};
372
373	hdlcd: hdlcd@7ff60000 {
374		compatible = "arm,hdlcd";
375		reg = <0x0 0x7ff60000 0x0 0x1000>;
376		interrupts = <0x0 117 0x4>;
377		clocks = <&fake_hdlcd_clk>;
378		clock-names = "pxlclk";
379		status = "disabled";
380
381		port {
382			hdlcd_out: endpoint {
383				remote-endpoint = <&vencoder_in>;
384			};
385		};
386	};
387
388	fake_hdlcd_clk: fake-hdlcd-clk {
389		compatible = "fixed-clock";
390		#clock-cells = <0>;
391		clock-frequency = <25175000>;
392		clock-output-names = "pxlclk";
393	};
394
395	ethernet@18000000 {
396		compatible = "smsc,lan91c111";
397		reg = <0x0 0x18000000 0x0 0x10000>;
398		interrupts = <0 109 4>;
399	};
400
401	kmi@1c060000 {
402		compatible = "arm,pl050", "arm,primecell";
403		reg = <0x0 0x001c060000 0x0 0x1000>;
404		interrupts = <0 197 4>;
405		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
406		clock-names = "KMIREFCLK", "apb_pclk";
407	};
408
409	kmi@1c070000 {
410		compatible = "arm,pl050", "arm,primecell";
411		reg = <0x0 0x001c070000 0x0 0x1000>;
412		interrupts = <0 103 4>;
413		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
414		clock-names = "KMIREFCLK", "apb_pclk";
415	};
416
417	bp_clock24mhz: clock24mhz {
418		compatible = "fixed-clock";
419		#clock-cells = <0>;
420		clock-frequency = <24000000>;
421		clock-output-names = "bp:clock24mhz";
422	};
423
424	virtio_block@1c130000 {
425		compatible = "virtio,mmio";
426		reg = <0x0 0x1c130000 0x0 0x200>;
427		interrupts = <0 204 4>;
428	};
429
430	sysreg: sysreg@1c010000 {
431		compatible = "arm,vexpress-sysreg";
432		reg = <0x0 0x001c010000 0x0 0x1000>;
433		gpio-controller;
434		#gpio-cells = <2>;
435	};
436
437	fixed_3v3: v2m-3v3 {
438		compatible = "regulator-fixed";
439		regulator-name = "3V3";
440		regulator-min-microvolt = <3300000>;
441		regulator-max-microvolt = <3300000>;
442		regulator-always-on;
443	};
444
445	mmci@1c050000 {
446		compatible = "arm,pl180", "arm,primecell";
447		reg = <0x0 0x001c050000 0x0 0x1000>;
448		interrupts = <0 107 0x4>,
449			     <0 108 0x4>;
450		cd-gpios = <&sysreg 0 0>;
451		wp-gpios = <&sysreg 1 0>;
452		bus-width = <8>;
453		max-frequency = <12000000>;
454		vmmc-supply = <&fixed_3v3>;
455		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
456		clock-names = "mclk", "apb_pclk";
457	};
458
459	gpu_clk: gpu_clk {
460		compatible = "fixed-clock";
461		#clock-cells = <0>;
462		clock-frequency = <1000000000>;
463	};
464
465	gpu_core_clk: gpu_core_clk {
466		compatible = "fixed-clock";
467		#clock-cells = <0>;
468		clock-frequency = <1000000000>;
469	};
470
471	gpu: gpu@2d000000 {
472		compatible = "arm,mali-midgard";
473		reg = <0x0 0x2d000000 0x0 0x200000>;
474		interrupts = <0 66 4>, <0 67 4>, <0 65 4>;
475		interrupt-names = "JOB", "MMU", "GPU";
476		clocks = <&gpu_clk>, <&gpu_core_clk>;
477		clock-names = "clk_mali", "shadercores";
478		iommus = <&smmu_700 0x200>;
479		operating-points = <
480			/* KHz uV */
481			50000 820000
482		>;
483	};
484
485	power_model@simple {
486		/*
487		 * Numbers used are irrelevant to Titan,
488		 * it helps suppressing the kernel warnings.
489		 */
490		compatible = "arm,mali-simple-power-model";
491		static-coefficient = <2427750>;
492		dynamic-coefficient = <4687>;
493		ts = <20000 2000 (-20) 2>;
494		thermal-zone = "";
495	};
496
497	smmu_700: smmu_700@3f000000 {
498		#iommu-cells = <1>;
499		compatible = "arm,smmu-v3";
500		reg = <0x0 0x3f000000 0x0 0x5000000>;
501		dma-coherent;
502	};
503
504	dp0: display@2cc00000 {
505		#address-cells = <1>;
506		#size-cells = <0>;
507		compatible = "arm,mali-d71";
508		reg = <0 0x2cc00000 0 0x20000>;
509		interrupts = <0 69 4>;
510		interrupt-names = "DPU";
511		clocks = <&scmi_clk 0>;
512		clock-names = "aclk";
513		iommus = <&smmu_700 0x100>;
514		pl0: pipeline@0 {
515			reg = <0>;
516			clocks = <&scmi_clk 1>;
517			clock-names = "pxclk";
518			pl_id = <0>;
519			ports {
520				#address-cells = <1>;
521				#size-cells = <0>;
522				port@0 {
523					reg = <0>;
524					dp_pl0_out0: endpoint {
525						remote-endpoint = <&vencoder_in>;
526					};
527				};
528			};
529		};
530
531		pl1: pipeline@1 {
532			reg = <1>;
533			clocks = <&scmi_clk 2>;
534			clock-names = "pxclk";
535			pl_id = <1>;
536			ports {
537				#address-cells = <1>;
538				#size-cells = <0>;
539				port@0 {
540					reg = <0>;
541				};
542			};
543		};
544	};
545
546	/*
547	 * L3 cache in the DSU is the Memory System Component (MSC)
548	 * The MPAM registers are accessed through utility bus in the DSU
549	 */
550	msc0 {
551		compatible = "arm,mpam-msc";
552		reg = <0x1 0x00010000 0x0 0x2000>;
553	};
554
555	ete0 {
556		compatible = "arm,embedded-trace-extension";
557		cpu = <&CPU0>;
558	};
559
560	ete1 {
561		compatible = "arm,embedded-trace-extension";
562		cpu = <&CPU1>;
563	};
564
565	ete2 {
566		compatible = "arm,embedded-trace-extension";
567		cpu = <&CPU2>;
568	};
569
570	ete3 {
571		compatible = "arm,embedded-trace-extension";
572		cpu = <&CPU3>;
573	};
574
575	ete4 {
576		compatible = "arm,embedded-trace-extension";
577		cpu = <&CPU4>;
578	};
579
580	ete5 {
581		compatible = "arm,embedded-trace-extension";
582		cpu = <&CPU5>;
583	};
584
585	ete6 {
586		compatible = "arm,embedded-trace-extension";
587		cpu = <&CPU6>;
588	};
589
590	ete7 {
591		compatible = "arm,embedded-trace-extension";
592		cpu = <&CPU7>;
593	};
594
595	trbe0 {
596		compatible = "arm,trace-buffer-extension";
597		interrupts = <1 2 4>;
598	};
599};
600