1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved 4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 5 * Copyright (C) 2020 Marek Vasut <marex@denx.de> 6 * Copyright (C) 2022 DH electronics GmbH 7 */ 8 9#include "stm32mp15-pinctrl.dtsi" 10#include "stm32mp15xxaa-pinctrl.dtsi" 11#include <dt-bindings/clock/stm32mp1-clksrc.h> 12#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" 13 14/ { 15 memory@c0000000 { 16 device_type = "memory"; 17 reg = <0xc0000000 0x40000000>; 18 }; 19}; 20 21&cpu0 { 22 cpu-supply = <&vddcore>; 23}; 24 25&cpu1 { 26 cpu-supply = <&vddcore>; 27}; 28 29&hash1 { 30 status = "okay"; 31}; 32 33&i2c4 { 34 pinctrl-names = "default"; 35 pinctrl-0 = <&i2c4_pins_a>; 36 i2c-scl-rising-time-ns = <185>; 37 i2c-scl-falling-time-ns = <20>; 38 status = "okay"; 39 40 pmic: stpmic@33 { 41 compatible = "st,stpmic1"; 42 reg = <0x33>; 43 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; 44 interrupt-controller; 45 #interrupt-cells = <2>; 46 status = "okay"; 47 48 regulators { 49 compatible = "st,stpmic1-regulators"; 50 ldo1-supply = <&v3v3>; 51 ldo2-supply = <&v3v3>; 52 ldo3-supply = <&vdd_ddr>; 53 ldo5-supply = <&v3v3>; 54 ldo6-supply = <&v3v3>; 55 pwr_sw1-supply = <&bst_out>; 56 pwr_sw2-supply = <&bst_out>; 57 58 vddcore: buck1 { 59 regulator-name = "vddcore"; 60 regulator-min-microvolt = <1200000>; 61 regulator-max-microvolt = <1350000>; 62 regulator-always-on; 63 regulator-initial-mode = <0>; 64 regulator-over-current-protection; 65 }; 66 67 vdd_ddr: buck2 { 68 regulator-name = "vdd_ddr"; 69 regulator-min-microvolt = <1350000>; 70 regulator-max-microvolt = <1350000>; 71 regulator-always-on; 72 regulator-initial-mode = <0>; 73 regulator-over-current-protection; 74 }; 75 76 vdd: buck3 { 77 regulator-name = "vdd"; 78 regulator-min-microvolt = <3300000>; 79 regulator-max-microvolt = <3300000>; 80 regulator-always-on; 81 regulator-initial-mode = <0>; 82 regulator-over-current-protection; 83 }; 84 85 v3v3: buck4 { 86 regulator-name = "v3v3"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-always-on; 90 regulator-over-current-protection; 91 regulator-initial-mode = <0>; 92 }; 93 94 vdda: ldo1 { 95 regulator-name = "vdda"; 96 regulator-min-microvolt = <2900000>; 97 regulator-max-microvolt = <2900000>; 98 }; 99 100 v2v8: ldo2 { 101 regulator-name = "v2v8"; 102 regulator-min-microvolt = <2800000>; 103 regulator-max-microvolt = <2800000>; 104 }; 105 106 vtt_ddr: ldo3 { 107 regulator-name = "vtt_ddr"; 108 regulator-always-on; 109 regulator-over-current-protection; 110 st,regulator-sink-source; 111 }; 112 113 vdd_usb: ldo4 { 114 regulator-name = "vdd_usb"; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 }; 118 119 vdd_sd: ldo5 { 120 regulator-name = "vdd_sd"; 121 regulator-min-microvolt = <2900000>; 122 regulator-max-microvolt = <2900000>; 123 regulator-boot-on; 124 }; 125 126 v1v8: ldo6 { 127 regulator-name = "v1v8"; 128 regulator-min-microvolt = <1800000>; 129 regulator-max-microvolt = <1800000>; 130 regulator-enable-ramp-delay = <300000>; 131 }; 132 133 vref_ddr: vref_ddr { 134 regulator-name = "vref_ddr"; 135 regulator-always-on; 136 }; 137 138 bst_out: boost { 139 regulator-name = "bst_out"; 140 }; 141 142 vbus_otg: pwr_sw1 { 143 regulator-name = "vbus_otg"; 144 regulator-active-discharge = <1>; 145 }; 146 147 vbus_sw: pwr_sw2 { 148 regulator-name = "vbus_sw"; 149 regulator-active-discharge = <1>; 150 }; 151 }; 152 }; 153}; 154 155&iwdg2 { 156 timeout-sec = <32>; 157 status = "okay"; 158}; 159 160&pwr_regulators { 161 vdd-supply = <&vdd>; 162 vdd_3v3_usbfs-supply = <&vdd_usb>; 163}; 164 165&qspi { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; 168 reg = <0x58003000 0x1000>, <0x70000000 0x200000>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 status = "okay"; 172 173 flash0: flash@0 { 174 compatible = "jedec,spi-nor"; 175 reg = <0>; 176 spi-rx-bus-width = <4>; 177 spi-max-frequency = <50000000>; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 }; 181}; 182 183&rcc { 184 st,clksrc = < 185 CLK_MPU_PLL1P 186 CLK_AXI_PLL2P 187 CLK_MCU_PLL3P 188 CLK_PLL12_HSE 189 CLK_PLL3_HSE 190 CLK_PLL4_HSE 191 CLK_RTC_LSE 192 CLK_MCO1_DISABLED 193 CLK_MCO2_DISABLED 194 >; 195 196 st,clkdiv = < 197 1 /*MPU*/ 198 0 /*AXI*/ 199 0 /*MCU*/ 200 1 /*APB1*/ 201 1 /*APB2*/ 202 1 /*APB3*/ 203 1 /*APB4*/ 204 2 /*APB5*/ 205 23 /*RTC*/ 206 0 /*MCO1*/ 207 0 /*MCO2*/ 208 >; 209 210 st,pkcs = < 211 CLK_CKPER_HSE 212 CLK_FMC_ACLK 213 CLK_QSPI_ACLK 214 CLK_ETH_DISABLED 215 CLK_SDMMC12_PLL4P 216 CLK_DSI_DSIPLL 217 CLK_STGEN_HSE 218 CLK_USBPHY_HSE 219 CLK_SPI2S1_PLL3Q 220 CLK_SPI2S23_PLL3Q 221 CLK_SPI45_HSI 222 CLK_SPI6_HSI 223 CLK_I2C46_HSI 224 CLK_SDMMC3_PLL4P 225 CLK_USBO_USBPHY 226 CLK_ADC_CKPER 227 CLK_CEC_LSE 228 CLK_I2C12_HSI 229 CLK_I2C35_HSI 230 CLK_UART1_HSI 231 CLK_UART24_HSI 232 CLK_UART35_HSI 233 CLK_UART6_HSI 234 CLK_UART78_HSI 235 CLK_SPDIF_PLL4P 236 CLK_FDCAN_PLL4R 237 CLK_SAI1_PLL3Q 238 CLK_SAI2_PLL3Q 239 CLK_SAI3_PLL3Q 240 CLK_SAI4_PLL3Q 241 CLK_RNG1_LSI 242 CLK_RNG2_LSI 243 CLK_LPTIM1_PCLK1 244 CLK_LPTIM23_PCLK3 245 CLK_LPTIM45_LSE 246 >; 247 248 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 249 pll1: st,pll@0 { 250 compatible = "st,stm32mp1-pll"; 251 reg = <0>; 252 cfg = <2 80 0 0 0 PQR(1,0,0)>; 253 frac = <0x800>; 254 }; 255 256 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 257 pll2: st,pll@1 { 258 compatible = "st,stm32mp1-pll"; 259 reg = <1>; 260 cfg = <2 65 1 0 0 PQR(1,1,1)>; 261 frac = <0x1400>; 262 }; 263 264 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 265 pll3: st,pll@2 { 266 compatible = "st,stm32mp1-pll"; 267 reg = <2>; 268 cfg = <1 33 1 16 36 PQR(1,1,1)>; 269 frac = <0x1a04>; 270 }; 271 272 /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ 273 pll4: st,pll@3 { 274 compatible = "st,stm32mp1-pll"; 275 reg = <3>; 276 cfg = <3 98 5 7 5 PQR(1,1,1)>; 277 }; 278}; 279 280&rng1 { 281 status = "okay"; 282}; 283 284&rtc { 285 status = "okay"; 286}; 287
