1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
4 * Copyright (C) 2022 DH electronics GmbH
5 */
6
7#include "stm32mp15-pinctrl.dtsi"
8#include "stm32mp15xxaa-pinctrl.dtsi"
9#include <dt-bindings/clock/stm32mp1-clksrc.h>
10#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
11
12/ {
13	memory@c0000000 {
14		device_type = "memory";
15		reg = <0xC0000000 0x40000000>;
16	};
17};
18
19&bsec {
20	board_id: board_id@ec {
21		reg = <0xec 0x4>;
22		st,non-secure-otp;
23	};
24};
25
26&cpu0 {
27	cpu-supply = <&vddcore>;
28};
29
30&cpu1 {
31	cpu-supply = <&vddcore>;
32};
33
34&hash1 {
35	status = "okay";
36};
37
38&i2c4 {
39	pinctrl-names = "default";
40	pinctrl-0 = <&i2c4_pins_a>;
41	i2c-scl-rising-time-ns = <185>;
42	i2c-scl-falling-time-ns = <20>;
43	status = "okay";
44
45	pmic: stpmic@33 {
46		compatible = "st,stpmic1";
47		reg = <0x33>;
48		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
49		interrupt-controller;
50		#interrupt-cells = <2>;
51		status = "okay";
52
53		regulators {
54			compatible = "st,stpmic1-regulators";
55			ldo1-supply = <&v3v3>;
56			ldo2-supply = <&v3v3>;
57			ldo3-supply = <&vdd_ddr>;
58			ldo5-supply = <&v3v3>;
59			ldo6-supply = <&v3v3>;
60			pwr_sw1-supply = <&bst_out>;
61			pwr_sw2-supply = <&bst_out>;
62
63			vddcore: buck1 {
64				regulator-name = "vddcore";
65				regulator-min-microvolt = <1200000>;
66				regulator-max-microvolt = <1350000>;
67				regulator-always-on;
68				regulator-initial-mode = <0>;
69				regulator-over-current-protection;
70			};
71
72			vdd_ddr: buck2 {
73				regulator-name = "vdd_ddr";
74				regulator-min-microvolt = <1350000>;
75				regulator-max-microvolt = <1350000>;
76				regulator-always-on;
77				regulator-initial-mode = <0>;
78				regulator-over-current-protection;
79			};
80
81			vdd: buck3 {
82				regulator-name = "vdd";
83				regulator-min-microvolt = <3300000>;
84				regulator-max-microvolt = <3300000>;
85				regulator-always-on;
86				st,mask-reset;
87				regulator-initial-mode = <0>;
88				regulator-over-current-protection;
89			};
90
91			v3v3: buck4 {
92				regulator-name = "v3v3";
93				regulator-min-microvolt = <3300000>;
94				regulator-max-microvolt = <3300000>;
95				regulator-always-on;
96				regulator-over-current-protection;
97				regulator-initial-mode = <0>;
98			};
99
100			vdda: ldo1 {
101				regulator-name = "vdda";
102				regulator-min-microvolt = <2900000>;
103				regulator-max-microvolt = <2900000>;
104				regulator-always-on;
105			};
106
107			v2v8: ldo2 {
108				regulator-name = "v2v8";
109				regulator-min-microvolt = <2800000>;
110				regulator-max-microvolt = <2800000>;
111			};
112
113			vtt_ddr: ldo3 {
114				regulator-name = "vtt_ddr";
115				regulator-always-on;
116				regulator-over-current-protection;
117				st,regulator-sink-source;
118			};
119
120			vdd_usb: ldo4 {
121				regulator-name = "vdd_usb";
122				regulator-min-microvolt = <3300000>;
123				regulator-max-microvolt = <3300000>;
124			};
125
126			vdd_sd: ldo5 {
127				regulator-name = "vdd_sd";
128				regulator-min-microvolt = <2900000>;
129				regulator-max-microvolt = <2900000>;
130				regulator-boot-on;
131			};
132
133			v1v8: ldo6 {
134				regulator-name = "v1v8";
135				regulator-min-microvolt = <1800000>;
136				regulator-max-microvolt = <1800000>;
137			};
138
139			vref_ddr: vref_ddr {
140				regulator-name = "vref_ddr";
141				regulator-always-on;
142			};
143
144			bst_out: boost {
145				regulator-name = "bst_out";
146			};
147
148			vbus_otg: pwr_sw1 {
149				regulator-name = "vbus_otg";
150			};
151
152			vbus_sw: pwr_sw2 {
153				regulator-name = "vbus_sw";
154				regulator-active-discharge = <1>;
155			};
156		};
157	};
158};
159
160&iwdg2 {
161	timeout-sec = <32>;
162	status = "okay";
163};
164
165&pwr_regulators {
166	vdd-supply = <&vdd>;
167	vdd_3v3_usbfs-supply = <&vdd_usb>;
168};
169
170&qspi {
171	pinctrl-names = "default";
172	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
173	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
174	#address-cells = <1>;
175	#size-cells = <0>;
176	status = "okay";
177
178	flash0: flash@0 {
179		compatible = "jedec,spi-nor";
180		reg = <0>;
181		spi-rx-bus-width = <4>;
182		spi-max-frequency = <108000000>;
183		#address-cells = <1>;
184		#size-cells = <1>;
185	};
186};
187
188&rcc {
189	st,clksrc = <
190		CLK_MPU_PLL1P
191		CLK_AXI_PLL2P
192		CLK_MCU_PLL3P
193		CLK_PLL12_HSE
194		CLK_PLL3_HSE
195		CLK_PLL4_HSE
196		CLK_RTC_LSE
197		CLK_MCO1_DISABLED
198		CLK_MCO2_PLL4P
199	>;
200
201	st,clkdiv = <
202		1 /*MPU*/
203		0 /*AXI*/
204		0 /*MCU*/
205		1 /*APB1*/
206		1 /*APB2*/
207		1 /*APB3*/
208		1 /*APB4*/
209		2 /*APB5*/
210		23 /*RTC*/
211		0 /*MCO1*/
212		1 /*MCO2*/
213	>;
214
215	st,pkcs = <
216		CLK_CKPER_HSE
217		CLK_FMC_ACLK
218		CLK_QSPI_ACLK
219		CLK_ETH_PLL4P
220		CLK_SDMMC12_PLL4P
221		CLK_DSI_DSIPLL
222		CLK_STGEN_HSE
223		CLK_USBPHY_HSE
224		CLK_SPI2S1_PLL3Q
225		CLK_SPI2S23_PLL3Q
226		CLK_SPI45_HSI
227		CLK_SPI6_HSI
228		CLK_I2C46_HSI
229		CLK_SDMMC3_PLL4P
230		CLK_USBO_USBPHY
231		CLK_ADC_CKPER
232		CLK_CEC_LSE
233		CLK_I2C12_HSI
234		CLK_I2C35_HSI
235		CLK_UART1_HSI
236		CLK_UART24_HSI
237		CLK_UART35_HSI
238		CLK_UART6_HSI
239		CLK_UART78_HSI
240		CLK_SPDIF_PLL4P
241		CLK_FDCAN_PLL4R
242		CLK_SAI1_PLL3Q
243		CLK_SAI2_PLL3Q
244		CLK_SAI3_PLL3Q
245		CLK_SAI4_PLL3Q
246		CLK_RNG1_LSI
247		CLK_RNG2_LSI
248		CLK_LPTIM1_PCLK1
249		CLK_LPTIM23_PCLK3
250		CLK_LPTIM45_LSE
251	>;
252
253	/* VCO = 1300.0 MHz => P = 650 (CPU) */
254	pll1: st,pll@0 {
255		compatible = "st,stm32mp1-pll";
256		reg = <0>;
257		cfg = <2 80 0 0 0 PQR(1,0,0)>;
258		frac = <0x800>;
259	};
260
261	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
262	pll2: st,pll@1 {
263		compatible = "st,stm32mp1-pll";
264		reg = <1>;
265		cfg = <2 65 1 0 0 PQR(1,1,1)>;
266		frac = <0x1400>;
267	};
268
269	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
270	pll3: st,pll@2 {
271		compatible = "st,stm32mp1-pll";
272		reg = <2>;
273		cfg = <1 33 1 16 36 PQR(1,1,1)>;
274		frac = <0x1a04>;
275	};
276
277	/* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
278	pll4: st,pll@3 {
279		compatible = "st,stm32mp1-pll";
280		reg = <3>;
281		cfg = <1 49 5 11 11 PQR(1,1,1)>;
282	};
283};
284
285&rng1 {
286	status = "okay";
287};
288
289&rtc {
290	status = "okay";
291};
292
293&sdmmc1 {
294	pinctrl-names = "default";
295	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
296	disable-wp;
297	st,sig-dir;
298	st,neg-edge;
299	bus-width = <4>;
300	vmmc-supply = <&vdd_sd>;
301	status = "okay";
302};
303
304&sdmmc1_b4_pins_a {
305	/*
306	 * SD bus pull-up resistors:
307	 * - optional on SoMs with SD voltage translator
308	 * - mandatory on SoMs without SD voltage translator
309	 */
310	pins1 {
311		bias-pull-up;
312	};
313	pins2 {
314		bias-pull-up;
315	};
316};
317
318&sdmmc2 {
319	pinctrl-names = "default";
320	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
321	non-removable;
322	no-sd;
323	no-sdio;
324	st,neg-edge;
325	bus-width = <8>;
326	vmmc-supply = <&v3v3>;
327	vqmmc-supply = <&v3v3>;
328	mmc-ddr-3_3v;
329	status = "okay";
330};
331
332&uart4 {
333	pinctrl-names = "default";
334	pinctrl-0 = <&uart4_pins_a>;
335	status = "okay";
336};
337