1// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 2/* 3 * ARM Ltd. Fast Models 4 * 5 * Architecture Envelope Model (AEM) ARMv8-A 6 * ARMAEMv8AMPCT 7 * 8 * RTSM_VE_AEMv8A.lisa 9 * 10 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <services/sdei_flags.h> 15 16#define LEVEL 0 17#define EDGE 2 18#define SDEI_NORMAL 0x70 19#define HIGHEST_SEC 0 20 21#include "rtsm_ve-motherboard.dtsi" 22 23/ { 24 model = "FVP Base"; 25 compatible = "arm,fvp-base", "arm,vexpress"; 26 interrupt-parent = <&gic>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30#if (ENABLE_RME == 1) 31 chosen { bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";}; 32#else 33 chosen {}; 34#endif 35 36 aliases { 37 serial0 = &v2m_serial0; 38 serial1 = &v2m_serial1; 39 serial2 = &v2m_serial2; 40 serial3 = &v2m_serial3; 41 }; 42 43 psci { 44 compatible = "arm,psci-1.0", "arm,psci-0.2"; 45 method = "smc"; 46 max-pwr-lvl = <2>; 47 }; 48 49#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF 50 firmware { 51#if SDEI_IN_FCONF 52 sdei { 53 compatible = "arm,sdei-1.0"; 54 method = "smc"; 55 private_event_count = <3>; 56 shared_event_count = <3>; 57 /* 58 * Each event descriptor has typically 3 fields: 59 * 1. Event number 60 * 2. Interrupt number the event is bound to or 61 * if event is dynamic, specified as SDEI_DYN_IRQ 62 * 3. Bit map of event flags 63 */ 64 private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 65 <1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 66 <1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 67 shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 68 <2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 69 <2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 70 }; 71#endif /* SDEI_IN_FCONF */ 72 73#if SEC_INT_DESC_IN_FCONF 74 sec_interrupts { 75 compatible = "arm,secure_interrupt_desc"; 76 /* Number of G0 and G1 secure interrupts defined by the platform */ 77 g0_intr_cnt = <2>; 78 g1s_intr_cnt = <9>; 79 /* 80 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 81 * terminology. Each interrupt property descriptor has 3 fields: 82 * 1. Interrupt number 83 * 2. Interrupt priority 84 * 3. Type of interrupt (Edge or Level configured) 85 */ 86 g0_intr_desc = < 8 SDEI_NORMAL EDGE>, 87 <14 HIGHEST_SEC EDGE>; 88 89 g1s_intr_desc = < 9 HIGHEST_SEC EDGE>, 90 <10 HIGHEST_SEC EDGE>, 91 <11 HIGHEST_SEC EDGE>, 92 <12 HIGHEST_SEC EDGE>, 93 <13 HIGHEST_SEC EDGE>, 94 <15 HIGHEST_SEC EDGE>, 95 <29 HIGHEST_SEC LEVEL>, 96 <56 HIGHEST_SEC LEVEL>, 97 <57 HIGHEST_SEC LEVEL>; 98 }; 99#endif /* SEC_INT_DESC_IN_FCONF */ 100 }; 101#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */ 102 103 cpus { 104 #address-cells = <2>; 105 #size-cells = <0>; 106 107 CPU_MAP 108 109 idle-states { 110 entry-method = "psci"; 111 112 CPU_SLEEP_0: cpu-sleep-0 { 113 compatible = "arm,idle-state"; 114 local-timer-stop; 115 arm,psci-suspend-param = <0x0010000>; 116 entry-latency-us = <40>; 117 exit-latency-us = <100>; 118 min-residency-us = <150>; 119 }; 120 121 CLUSTER_SLEEP_0: cluster-sleep-0 { 122 compatible = "arm,idle-state"; 123 local-timer-stop; 124 arm,psci-suspend-param = <0x1010000>; 125 entry-latency-us = <500>; 126 exit-latency-us = <1000>; 127 min-residency-us = <2500>; 128 }; 129 }; 130 131 CPUS 132 133 L2_0: l2-cache0 { 134 compatible = "cache"; 135 }; 136 }; 137 138 memory@80000000 { 139 device_type = "memory"; 140#if (ENABLE_RME == 1) 141 reg = <0x00000000 0x80000000 0 0x7C000000>, 142 <0x00000008 0x80000000 0 0x80000000>; 143#else 144 reg = <0x00000000 0x80000000 0 0x7F000000>, 145 <0x00000008 0x80000000 0 0x80000000>; 146#endif 147 }; 148 149 reserved-memory { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 /* Chipselect 2,00000000 is physically at 0x18000000 */ 155 vram: vram@18000000 { 156 /* 8 MB of designated video RAM */ 157 compatible = "shared-dma-pool"; 158 reg = <0x00000000 0x18000000 0 0x00800000>; 159 no-map; 160 }; 161 }; 162 163 timer { 164 compatible = "arm,armv8-timer"; 165 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 166 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 169 clock-frequency = <100000000>; 170 }; 171 172 timer@2a810000 { 173 compatible = "arm,armv7-timer-mem"; 174 reg = <0x0 0x2a810000 0x0 0x10000>; 175 clock-frequency = <100000000>; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges = <0x0 0x0 0x2a810000 0x100000>; 179 180 frame@2a830000 { 181 frame-number = <1>; 182 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 183 reg = <0x20000 0x10000>; 184 }; 185 }; 186 187 pmu { 188 compatible = "arm,armv8-pmuv3"; 189 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 190 }; 191 192 panel { 193 compatible = "arm,rtsm-display"; 194 port { 195 panel_in: endpoint { 196 remote-endpoint = <&clcd_pads>; 197 }; 198 }; 199 }; 200 201 bus@8000000 { 202 #interrupt-cells = <1>; 203 interrupt-map-mask = <0 0 63>; 204 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 205 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 206 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 207 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 208 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 209 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 210 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 211 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 212 <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 213 <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 214 <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 215 <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 216 <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 217 <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 218 <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 219 <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 220 <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 221 <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 222 <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 223 <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 224 <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 225 <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 226 <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 227 <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 228 <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 229 <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 230 <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 231 <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 232 <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 233 <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 234 <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 235 <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 236 <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 237 <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 238 <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 239 <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 240 <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 241 <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 242 <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 243 <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 244 <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 245 <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 246 <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 247 }; 248}; 249
