1/* 2 * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <bl31/sync_handle.h> 14#include <common/runtime_svc.h> 15#include <context.h> 16#include <el3_common_macros.S> 17#include <lib/el3_runtime/cpu_data.h> 18#include <lib/smccc.h> 19 20 .globl runtime_exceptions 21 22 .globl sync_exception_sp_el0 23 .globl irq_sp_el0 24 .globl fiq_sp_el0 25 .globl serror_sp_el0 26 27 .globl sync_exception_sp_elx 28 .globl irq_sp_elx 29 .globl fiq_sp_elx 30 .globl serror_sp_elx 31 32 .globl sync_exception_aarch64 33 .globl irq_aarch64 34 .globl fiq_aarch64 35 .globl serror_aarch64 36 37 .globl sync_exception_aarch32 38 .globl irq_aarch32 39 .globl fiq_aarch32 40 .globl serror_aarch32 41 42 /* 43 * Save LR and make x30 available as most of the routines in vector entry 44 * need a free register 45 */ 46 .macro save_x30 47 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 48 .endm 49 50 /* 51 * Macro that prepares entry to EL3 upon taking an exception. 52 * 53 * With RAS_FFH_SUPPORT, this macro synchronizes pending errors with an 54 * ESB instruction. When an error is thus synchronized, the handling is 55 * delegated to platform EA handler. 56 * 57 * Without RAS_FFH_SUPPORT, this macro synchronizes pending errors using 58 * a DSB, unmasks Asynchronous External Aborts and saves X30 before 59 * setting the flag CTX_IS_IN_EL3. 60 */ 61 .macro check_and_unmask_ea 62#if RAS_FFH_SUPPORT 63 /* Synchronize pending External Aborts */ 64 esb 65 66 /* Unmask the SError interrupt */ 67 msr daifclr, #DAIF_ABT_BIT 68 69 /* Check for SErrors synchronized by the ESB instruction */ 70 mrs x30, DISR_EL1 71 tbz x30, #DISR_A_BIT, 1f 72 73 /* 74 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 75 * Also save PMCR_EL0 and set the PSTATE to a known state. 76 */ 77 bl prepare_el3_entry 78 79 bl handle_lower_el_ea_esb 80 81 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ 82 bl restore_gp_pmcr_pauth_regs 831: 84#else 85 /* 86 * Note 1: The explicit DSB at the entry of various exception vectors 87 * for handling exceptions from lower ELs can inadvertently trigger an 88 * SError exception in EL3 due to pending asynchronous aborts in lower 89 * ELs. This will end up being handled by serror_sp_elx which will 90 * ultimately panic and die. 91 * The way to workaround is to update a flag to indicate if the exception 92 * truly came from EL3. This flag is allocated in the cpu_context 93 * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3" 94 * This is not a bullet proof solution to the problem at hand because 95 * we assume the instructions following "isb" that help to update the 96 * flag execute without causing further exceptions. 97 */ 98 99 /* 100 * For SoCs which do not implement RAS, use DSB as a barrier to 101 * synchronize pending external aborts. 102 */ 103 dsb sy 104 105 /* Unmask the SError interrupt */ 106 msr daifclr, #DAIF_ABT_BIT 107 108 /* Use ISB for the above unmask operation to take effect immediately */ 109 isb 110 111 /* Refer Note 1. */ 112 mov x30, #1 113 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] 114 dmb sy 115#endif 116 .endm 117 118 /* --------------------------------------------------------------------- 119 * This macro handles Synchronous exceptions. 120 * Only SMC exceptions are supported. 121 * --------------------------------------------------------------------- 122 */ 123 .macro handle_sync_exception 124#if ENABLE_RUNTIME_INSTRUMENTATION 125 /* 126 * Read the timestamp value and store it in per-cpu data. The value 127 * will be extracted from per-cpu data by the C level SMC handler and 128 * saved to the PMF timestamp region. 129 */ 130 mrs x30, cntpct_el0 131 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 132 mrs x29, tpidr_el3 133 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 134 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 135#endif 136 137 mrs x30, esr_el3 138 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 139 140 /* Handle SMC exceptions separately from other synchronous exceptions */ 141 cmp x30, #EC_AARCH32_SMC 142 b.eq smc_handler32 143 144 cmp x30, #EC_AARCH64_SMC 145 b.eq sync_handler64 146 147 cmp x30, #EC_AARCH64_SYS 148 b.eq sync_handler64 149 150 /* Synchronous exceptions other than the above are assumed to be EA */ 151 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 152 b handle_lower_el_sync_ea 153 .endm 154 155 156 /* --------------------------------------------------------------------- 157 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 158 * interrupts. 159 * --------------------------------------------------------------------- 160 */ 161 .macro handle_interrupt_exception label 162 163 /* 164 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 165 * Also save PMCR_EL0 and set the PSTATE to a known state. 166 */ 167 bl prepare_el3_entry 168 169#if ENABLE_PAUTH 170 /* Load and program APIAKey firmware key */ 171 bl pauth_load_bl31_apiakey 172#endif 173 174 /* Save the EL3 system registers needed to return from this exception */ 175 mrs x0, spsr_el3 176 mrs x1, elr_el3 177 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 178 179 /* Switch to the runtime stack i.e. SP_EL0 */ 180 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 181 mov x20, sp 182 msr spsel, #MODE_SP_EL0 183 mov sp, x2 184 185 /* 186 * Find out whether this is a valid interrupt type. 187 * If the interrupt controller reports a spurious interrupt then return 188 * to where we came from. 189 */ 190 bl plat_ic_get_pending_interrupt_type 191 cmp x0, #INTR_TYPE_INVAL 192 b.eq interrupt_exit_\label 193 194 /* 195 * Get the registered handler for this interrupt type. 196 * A NULL return value could be 'cause of the following conditions: 197 * 198 * a. An interrupt of a type was routed correctly but a handler for its 199 * type was not registered. 200 * 201 * b. An interrupt of a type was not routed correctly so a handler for 202 * its type was not registered. 203 * 204 * c. An interrupt of a type was routed correctly to EL3, but was 205 * deasserted before its pending state could be read. Another 206 * interrupt of a different type pended at the same time and its 207 * type was reported as pending instead. However, a handler for this 208 * type was not registered. 209 * 210 * a. and b. can only happen due to a programming error. The 211 * occurrence of c. could be beyond the control of Trusted Firmware. 212 * It makes sense to return from this exception instead of reporting an 213 * error. 214 */ 215 bl get_interrupt_type_handler 216 cbz x0, interrupt_exit_\label 217 mov x21, x0 218 219 mov x0, #INTR_ID_UNAVAILABLE 220 221 /* Set the current security state in the 'flags' parameter */ 222 mrs x2, scr_el3 223 ubfx x1, x2, #0, #1 224 225 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 226 mov x2, x20 227 228 /* x3 will point to a cookie (not used now) */ 229 mov x3, xzr 230 231 /* Call the interrupt type handler */ 232 blr x21 233 234interrupt_exit_\label: 235 /* Return from exception, possibly in a different security state */ 236 b el3_exit 237 238 .endm 239 240 241vector_base runtime_exceptions 242 243 /* --------------------------------------------------------------------- 244 * Current EL with SP_EL0 : 0x0 - 0x200 245 * --------------------------------------------------------------------- 246 */ 247vector_entry sync_exception_sp_el0 248#ifdef MONITOR_TRAPS 249 stp x29, x30, [sp, #-16]! 250 251 mrs x30, esr_el3 252 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 253 254 /* Check for BRK */ 255 cmp x30, #EC_BRK 256 b.eq brk_handler 257 258 ldp x29, x30, [sp], #16 259#endif /* MONITOR_TRAPS */ 260 261 /* We don't expect any synchronous exceptions from EL3 */ 262 b report_unhandled_exception 263end_vector_entry sync_exception_sp_el0 264 265vector_entry irq_sp_el0 266 /* 267 * EL3 code is non-reentrant. Any asynchronous exception is a serious 268 * error. Loop infinitely. 269 */ 270 b report_unhandled_interrupt 271end_vector_entry irq_sp_el0 272 273 274vector_entry fiq_sp_el0 275 b report_unhandled_interrupt 276end_vector_entry fiq_sp_el0 277 278 279vector_entry serror_sp_el0 280 no_ret plat_handle_el3_ea 281end_vector_entry serror_sp_el0 282 283 /* --------------------------------------------------------------------- 284 * Current EL with SP_ELx: 0x200 - 0x400 285 * --------------------------------------------------------------------- 286 */ 287vector_entry sync_exception_sp_elx 288 /* 289 * This exception will trigger if anything went wrong during a previous 290 * exception entry or exit or while handling an earlier unexpected 291 * synchronous exception. There is a high probability that SP_EL3 is 292 * corrupted. 293 */ 294 b report_unhandled_exception 295end_vector_entry sync_exception_sp_elx 296 297vector_entry irq_sp_elx 298 b report_unhandled_interrupt 299end_vector_entry irq_sp_elx 300 301vector_entry fiq_sp_elx 302 b report_unhandled_interrupt 303end_vector_entry fiq_sp_elx 304 305vector_entry serror_sp_elx 306#if !RAS_FFH_SUPPORT 307 /* 308 * This will trigger if the exception was taken due to SError in EL3 or 309 * because of pending asynchronous external aborts from lower EL that got 310 * triggered due to explicit synchronization in EL3. Refer Note 1. 311 */ 312 /* Assumes SP_EL3 on entry */ 313 save_x30 314 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] 315 cbnz x30, 1f 316 317 /* Handle asynchronous external abort from lower EL */ 318 b handle_lower_el_async_ea 3191: 320#endif 321 no_ret plat_handle_el3_ea 322end_vector_entry serror_sp_elx 323 324 /* --------------------------------------------------------------------- 325 * Lower EL using AArch64 : 0x400 - 0x600 326 * --------------------------------------------------------------------- 327 */ 328vector_entry sync_exception_aarch64 329 /* 330 * This exception vector will be the entry point for SMCs and traps 331 * that are unhandled at lower ELs most commonly. SP_EL3 should point 332 * to a valid cpu context where the general purpose and system register 333 * state can be saved. 334 */ 335 save_x30 336 apply_at_speculative_wa 337 check_and_unmask_ea 338 handle_sync_exception 339end_vector_entry sync_exception_aarch64 340 341vector_entry irq_aarch64 342 save_x30 343 apply_at_speculative_wa 344 check_and_unmask_ea 345 handle_interrupt_exception irq_aarch64 346end_vector_entry irq_aarch64 347 348vector_entry fiq_aarch64 349 save_x30 350 apply_at_speculative_wa 351 check_and_unmask_ea 352 handle_interrupt_exception fiq_aarch64 353end_vector_entry fiq_aarch64 354 355vector_entry serror_aarch64 356 save_x30 357 apply_at_speculative_wa 358#if RAS_FFH_SUPPORT 359 msr daifclr, #DAIF_ABT_BIT 360#else 361 check_and_unmask_ea 362#endif 363 b handle_lower_el_async_ea 364 365end_vector_entry serror_aarch64 366 367 /* --------------------------------------------------------------------- 368 * Lower EL using AArch32 : 0x600 - 0x800 369 * --------------------------------------------------------------------- 370 */ 371vector_entry sync_exception_aarch32 372 /* 373 * This exception vector will be the entry point for SMCs and traps 374 * that are unhandled at lower ELs most commonly. SP_EL3 should point 375 * to a valid cpu context where the general purpose and system register 376 * state can be saved. 377 */ 378 save_x30 379 apply_at_speculative_wa 380 check_and_unmask_ea 381 handle_sync_exception 382end_vector_entry sync_exception_aarch32 383 384vector_entry irq_aarch32 385 save_x30 386 apply_at_speculative_wa 387 check_and_unmask_ea 388 handle_interrupt_exception irq_aarch32 389end_vector_entry irq_aarch32 390 391vector_entry fiq_aarch32 392 save_x30 393 apply_at_speculative_wa 394 check_and_unmask_ea 395 handle_interrupt_exception fiq_aarch32 396end_vector_entry fiq_aarch32 397 398vector_entry serror_aarch32 399 save_x30 400 apply_at_speculative_wa 401#if RAS_FFH_SUPPORT 402 msr daifclr, #DAIF_ABT_BIT 403#else 404 check_and_unmask_ea 405#endif 406 b handle_lower_el_async_ea 407 408end_vector_entry serror_aarch32 409 410#ifdef MONITOR_TRAPS 411 .section .rodata.brk_string, "aS" 412brk_location: 413 .asciz "Error at instruction 0x" 414brk_message: 415 .asciz "Unexpected BRK instruction with value 0x" 416#endif /* MONITOR_TRAPS */ 417 418 /* --------------------------------------------------------------------- 419 * The following code handles secure monitor calls. 420 * Depending upon the execution state from where the SMC has been 421 * invoked, it frees some general purpose registers to perform the 422 * remaining tasks. They involve finding the runtime service handler 423 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 424 * before calling the handler. 425 * 426 * Note that x30 has been explicitly saved and can be used here 427 * --------------------------------------------------------------------- 428 */ 429func sync_exception_handler 430smc_handler32: 431 /* Check whether aarch32 issued an SMC64 */ 432 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 433 434sync_handler64: 435 /* NOTE: The code below must preserve x0-x4 */ 436 437 /* 438 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 439 * Also save PMCR_EL0 and set the PSTATE to a known state. 440 */ 441 bl prepare_el3_entry 442 443#if ENABLE_PAUTH 444 /* Load and program APIAKey firmware key */ 445 bl pauth_load_bl31_apiakey 446#endif 447 448 /* 449 * Populate the parameters for the SMC handler. 450 * We already have x0-x4 in place. x5 will point to a cookie (not used 451 * now). x6 will point to the context structure (SP_EL3) and x7 will 452 * contain flags we need to pass to the handler. 453 */ 454 mov x5, xzr 455 mov x6, sp 456 457 /* 458 * Restore the saved C runtime stack value which will become the new 459 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 460 * structure prior to the last ERET from EL3. 461 */ 462 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 463 464 /* Switch to SP_EL0 */ 465 msr spsel, #MODE_SP_EL0 466 467 /* 468 * Save the SPSR_EL3 and ELR_EL3 in case there is a world 469 * switch during SMC handling. 470 * TODO: Revisit if all system registers can be saved later. 471 */ 472 mrs x16, spsr_el3 473 mrs x17, elr_el3 474 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 475 476 /* Load SCR_EL3 */ 477 mrs x18, scr_el3 478 479 /* check for system register traps */ 480 mrs x16, esr_el3 481 ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH 482 cmp x17, #EC_AARCH64_SYS 483 b.eq sysreg_handler64 484 485 /* Clear flag register */ 486 mov x7, xzr 487 488#if ENABLE_RME 489 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */ 490 ubfx x7, x18, #SCR_NSE_SHIFT, 1 491 492 /* 493 * Shift copied SCR_EL3.NSE bit by 5 to create space for 494 * SCR_EL3.NS bit. Bit 5 of the flag corresponds to 495 * the SCR_EL3.NSE bit. 496 */ 497 lsl x7, x7, #5 498#endif /* ENABLE_RME */ 499 500 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 501 bfi x7, x18, #0, #1 502 503 mov sp, x12 504 505 /* 506 * Per SMCCC documentation, bits [23:17] must be zero for Fast 507 * SMCs. Other values are reserved for future use. Ensure that 508 * these bits are zeroes, if not report as unknown SMC. 509 */ 510 tbz x0, #FUNCID_TYPE_SHIFT, 2f /* Skip check if its a Yield Call*/ 511 tst x0, #(FUNCID_FC_RESERVED_MASK << FUNCID_FC_RESERVED_SHIFT) 512 b.ne smc_unknown 513 514 /* 515 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID 516 * passed through x0. Copy the SVE hint bit to flags and mask the 517 * bit in smc_fid passed to the standard service dispatcher. 518 * A service/dispatcher can retrieve the SVE hint bit state from 519 * flags using the appropriate helper. 520 */ 5212: 522 bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK 523 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) 524 525 /* Get the unique owning entity number */ 526 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 527 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 528 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 529 530 /* Load descriptor index from array of indices */ 531 adrp x14, rt_svc_descs_indices 532 add x14, x14, :lo12:rt_svc_descs_indices 533 ldrb w15, [x14, x16] 534 535 /* Any index greater than 127 is invalid. Check bit 7. */ 536 tbnz w15, 7, smc_unknown 537 538 /* 539 * Get the descriptor using the index 540 * x11 = (base + off), w15 = index 541 * 542 * handler = (base + off) + (index << log2(size)) 543 */ 544 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 545 lsl w10, w15, #RT_SVC_SIZE_LOG2 546 ldr x15, [x11, w10, uxtw] 547 548 /* 549 * Call the Secure Monitor Call handler and then drop directly into 550 * el3_exit() which will program any remaining architectural state 551 * prior to issuing the ERET to the desired lower EL. 552 */ 553#if DEBUG 554 cbz x15, rt_svc_fw_critical_error 555#endif 556 blr x15 557 558 b el3_exit 559 560sysreg_handler64: 561 mov x0, x16 /* ESR_EL3, containing syndrome information */ 562 mov x1, x6 /* lower EL's context */ 563 mov x19, x6 /* save context pointer for after the call */ 564 mov sp, x12 /* EL3 runtime stack, as loaded above */ 565 566 /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */ 567 bl handle_sysreg_trap 568 /* 569 * returns: 570 * -1: unhandled trap, panic 571 * 0: handled trap, return to the trapping instruction (repeating it) 572 * 1: handled trap, return to the next instruction 573 */ 574 575 tst w0, w0 576 b.mi elx_panic /* negative return value: panic */ 577 b.eq 1f /* zero: do not change ELR_EL3 */ 578 579 /* advance the PC to continue after the instruction */ 580 ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] 581 add x1, x1, #4 582 str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] 5831: 584 b el3_exit 585 586smc_unknown: 587 /* 588 * Unknown SMC call. Populate return value with SMC_UNK and call 589 * el3_exit() which will restore the remaining architectural state 590 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET 591 * to the desired lower EL. 592 */ 593 mov x0, #SMC_UNK 594 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 595 b el3_exit 596 597smc_prohibited: 598 restore_ptw_el1_sys_regs 599 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 600 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 601 mov x0, #SMC_UNK 602 exception_return 603 604#if DEBUG 605rt_svc_fw_critical_error: 606 /* Switch to SP_ELx */ 607 msr spsel, #MODE_SP_ELX 608 no_ret report_unhandled_exception 609#endif 610endfunc sync_exception_handler 611 612 /* --------------------------------------------------------------------- 613 * The following code handles exceptions caused by BRK instructions. 614 * Following a BRK instruction, the only real valid cause of action is 615 * to print some information and panic, as the code that caused it is 616 * likely in an inconsistent internal state. 617 * 618 * This is initially intended to be used in conjunction with 619 * __builtin_trap. 620 * --------------------------------------------------------------------- 621 */ 622#ifdef MONITOR_TRAPS 623func brk_handler 624 /* Extract the ISS */ 625 mrs x10, esr_el3 626 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH 627 628 /* Ensure the console is initialized */ 629 bl plat_crash_console_init 630 631 adr x4, brk_location 632 bl asm_print_str 633 mrs x4, elr_el3 634 bl asm_print_hex 635 bl asm_print_newline 636 637 adr x4, brk_message 638 bl asm_print_str 639 mov x4, x10 640 mov x5, #28 641 bl asm_print_hex_bits 642 bl asm_print_newline 643 644 no_ret plat_panic_handler 645endfunc brk_handler 646#endif /* MONITOR_TRAPS */ 647
