1/*
2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15#if BL2_IN_XIP_MEM
16    ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
17    RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
18#else /* BL2_IN_XIP_MEM */
19    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
20#endif /* BL2_IN_XIP_MEM */
21
22#if SEPARATE_BL2_NOLOAD_REGION
23    RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START
24#else /* SEPARATE_BL2_NOLOAD_REGION */
25#   define RAM_NOLOAD RAM
26#endif /* SEPARATE_BL2_NOLOAD_REGION */
27}
28
29#if !BL2_IN_XIP_MEM
30#   define ROM RAM
31#endif /* !BL2_IN_XIP_MEM */
32
33SECTIONS {
34#if BL2_IN_XIP_MEM
35    . = BL2_RO_BASE;
36
37    ASSERT(. == ALIGN(PAGE_SIZE),
38        "BL2_RO_BASE address is not aligned on a page boundary.")
39#else /* BL2_IN_XIP_MEM */
40    . = BL2_BASE;
41
42    ASSERT(. == ALIGN(PAGE_SIZE),
43        "BL2_BASE address is not aligned on a page boundary.")
44#endif /* BL2_IN_XIP_MEM */
45
46#if SEPARATE_CODE_AND_RODATA
47    .text . : {
48        __TEXT_START__ = .;
49        __TEXT_RESIDENT_START__ = .;
50
51        *bl2_el3_entrypoint.o(.text*)
52        *(.text.asm.*)
53
54        __TEXT_RESIDENT_END__ = .;
55
56        *(SORT_BY_ALIGNMENT(.text*))
57        *(.vectors)
58
59        . = ALIGN(PAGE_SIZE);
60
61        __TEXT_END__ = .;
62    } >ROM
63
64    .rodata . : {
65        __RODATA_START__ = .;
66
67        *(SORT_BY_ALIGNMENT(.rodata*))
68
69        RODATA_COMMON
70
71        . = ALIGN(PAGE_SIZE);
72
73        __RODATA_END__ = .;
74    } >ROM
75
76    ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
77        "Resident part of BL2 has exceeded its limit.")
78#else /* SEPARATE_CODE_AND_RODATA */
79    .ro . : {
80        __RO_START__ = .;
81        __TEXT_RESIDENT_START__ = .;
82
83        *bl2_el3_entrypoint.o(.text*)
84        *(.text.asm.*)
85
86        __TEXT_RESIDENT_END__ = .;
87
88        *(SORT_BY_ALIGNMENT(.text*))
89        *(SORT_BY_ALIGNMENT(.rodata*))
90
91        RODATA_COMMON
92
93        *(.vectors)
94
95        __RO_END_UNALIGNED__ = .;
96
97        /*
98         * Memory page(s) mapped to this section will be marked as read-only,
99         * executable. No RW data from the next section must creep in. Ensure
100         * that the rest of the current memory page is unused.
101         */
102        . = ALIGN(PAGE_SIZE);
103
104        __RO_END__ = .;
105    } >ROM
106#endif /* SEPARATE_CODE_AND_RODATA */
107
108    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
109        "cpu_ops not defined for this platform.")
110
111#if BL2_IN_XIP_MEM
112    . = BL2_RW_BASE;
113
114    ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
115           "BL2_RW_BASE address is not aligned on a page boundary.")
116#endif /* BL2_IN_XIP_MEM */
117
118    __RW_START__ = .;
119
120    DATA_SECTION >RAM AT>ROM
121
122    __DATA_RAM_START__ = __DATA_START__;
123    __DATA_RAM_END__ = __DATA_END__;
124
125    RELA_SECTION >RAM
126
127#if SEPARATE_BL2_NOLOAD_REGION
128    SAVED_ADDR = .;
129
130    . = BL2_NOLOAD_START;
131
132    __BL2_NOLOAD_START__ = .;
133#endif /* SEPARATE_BL2_NOLOAD_REGION */
134
135    STACK_SECTION >RAM_NOLOAD
136    BSS_SECTION >RAM_NOLOAD
137    XLAT_TABLE_SECTION >RAM_NOLOAD
138
139#if SEPARATE_BL2_NOLOAD_REGION
140    __BL2_NOLOAD_END__ = .;
141
142    . = SAVED_ADDR;
143#endif /* SEPARATE_BL2_NOLOAD_REGION */
144
145#if USE_COHERENT_MEM
146    /*
147     * The base address of the coherent memory section must be page-aligned to
148     * guarantee that the coherent data are stored on their own pages and are
149     * not mixed with normal data.  This is required to set up the correct
150     * memory attributes for the coherent data page tables.
151     */
152    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
153        __COHERENT_RAM_START__ = .;
154
155        *(.tzfw_coherent_mem)
156
157        __COHERENT_RAM_END_UNALIGNED__ = .;
158
159        /*
160         * Memory page(s) mapped to this section will be marked as device
161         * memory. No other unexpected data must creep in. Ensure the rest of
162         * the current memory page is unused.
163         */
164        . = ALIGN(PAGE_SIZE);
165
166        __COHERENT_RAM_END__ = .;
167    } >RAM
168#endif /* USE_COHERENT_MEM */
169
170    __RW_END__ = .;
171    __BL2_END__ = .;
172
173    /DISCARD/ : {
174        *(.dynsym .dynstr .hash .gnu.hash)
175    }
176
177#if BL2_IN_XIP_MEM
178    __BL2_RAM_START__ = ADDR(.data);
179    __BL2_RAM_END__ = .;
180
181    __DATA_ROM_START__ = LOADADDR(.data);
182    __DATA_SIZE__ = SIZEOF(.data);
183
184    /*
185     * The .data section is the last PROGBITS section so its end marks the end
186     * of BL2's RO content in XIP memory.
187     */
188    __BL2_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
189
190    ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
191           "BL2's RO content has exceeded its limit.")
192#endif /* BL2_IN_XIP_MEM */
193
194    __BSS_SIZE__ = SIZEOF(.bss);
195
196#if USE_COHERENT_MEM
197    __COHERENT_RAM_UNALIGNED_SIZE__ =
198        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
199#endif /* USE_COHERENT_MEM */
200
201#if BL2_IN_XIP_MEM
202    ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
203#else /* BL2_IN_XIP_MEM */
204    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
205#endif /* BL2_IN_XIP_MEM */
206}
207