1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16}
17
18SECTIONS {
19    . = BL2_BASE;
20
21    ASSERT(. == ALIGN(PAGE_SIZE),
22        "BL2_BASE address is not aligned on a page boundary.")
23
24#if SEPARATE_CODE_AND_RODATA
25    .text . : {
26        __TEXT_START__ = .;
27
28#if ENABLE_RME
29        *bl2_rme_entrypoint.o(.text*)
30#else /* ENABLE_RME */
31        *bl2_entrypoint.o(.text*)
32#endif /* ENABLE_RME */
33
34        *(SORT_BY_ALIGNMENT(.text*))
35        *(.vectors)
36
37        . = ALIGN(PAGE_SIZE);
38
39        __TEXT_END__ = .;
40    } >RAM
41
42    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
43    .ARM.extab . : {
44        *(.ARM.extab* .gnu.linkonce.armextab.*)
45    } >RAM
46
47    .ARM.exidx . : {
48        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
49    } >RAM
50
51    .rodata . : {
52        __RODATA_START__ = .;
53
54        *(SORT_BY_ALIGNMENT(.rodata*))
55
56        RODATA_COMMON
57
58        . = ALIGN(PAGE_SIZE);
59
60        __RODATA_END__ = .;
61    } >RAM
62#else /* SEPARATE_CODE_AND_RODATA */
63    .ro . : {
64        __RO_START__ = .;
65
66        *bl2_entrypoint.o(.text*)
67        *(SORT_BY_ALIGNMENT(.text*))
68        *(SORT_BY_ALIGNMENT(.rodata*))
69
70        RODATA_COMMON
71
72        *(.vectors)
73
74        __RO_END_UNALIGNED__ = .;
75
76        /*
77         * Memory page(s) mapped to this section will be marked as read-only,
78         * executable. No RW data from the next section must creep in. Ensure
79         * that the rest of the current memory page is unused.
80         */
81        . = ALIGN(PAGE_SIZE);
82
83        __RO_END__ = .;
84    } >RAM
85#endif /* SEPARATE_CODE_AND_RODATA */
86
87    __RW_START__ = .;
88
89    DATA_SECTION >RAM
90    STACK_SECTION >RAM
91    BSS_SECTION >RAM
92    XLAT_TABLE_SECTION >RAM
93
94#if USE_COHERENT_MEM
95    /*
96     * The base address of the coherent memory section must be page-aligned to
97     * guarantee that the coherent data are stored on their own pages and are
98     * not mixed with normal data.  This is required to set up the correct
99     * memory attributes for the coherent data page tables.
100     */
101    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
102        __COHERENT_RAM_START__ = .;
103        *(.tzfw_coherent_mem)
104        __COHERENT_RAM_END_UNALIGNED__ = .;
105
106        /*
107         * Memory page(s) mapped to this section will be marked as device
108         * memory. No other unexpected data must creep in. Ensure the rest of
109         * the current memory page is unused.
110         */
111        . = ALIGN(PAGE_SIZE);
112
113        __COHERENT_RAM_END__ = .;
114    } >RAM
115#endif /* USE_COHERENT_MEM */
116
117    __RW_END__ = .;
118    __BL2_END__ = .;
119
120    __BSS_SIZE__ = SIZEOF(.bss);
121
122#if USE_COHERENT_MEM
123    __COHERENT_RAM_UNALIGNED_SIZE__ =
124        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
125#endif /* USE_COHERENT_MEM */
126
127    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
128}
129