1/*
2 * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * The .data section gets copied from ROM to RAM at runtime. Its LMA should be
9 * 16-byte aligned to allow efficient copying of 16-bytes aligned regions in it.
10 * Its VMA must be page-aligned as it marks the first read/write page.
11 */
12#define DATA_ALIGN	16
13
14#include <common/bl_common.ld.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
16
17OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
18OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
19ENTRY(bl1_entrypoint)
20
21MEMORY {
22    ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
23    RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
24}
25
26SECTIONS {
27    . = BL1_RO_BASE;
28
29    ASSERT(. == ALIGN(PAGE_SIZE),
30        "BL1_RO_BASE address is not aligned on a page boundary.")
31
32#if SEPARATE_CODE_AND_RODATA
33    .text . : {
34        __TEXT_START__ = .;
35
36        *bl1_entrypoint.o(.text*)
37        *(SORT_BY_ALIGNMENT(.text*))
38        *(.vectors)
39
40        . = ALIGN(PAGE_SIZE);
41
42        __TEXT_END__ = .;
43    } >ROM
44
45    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
46    .ARM.extab . : {
47        *(.ARM.extab* .gnu.linkonce.armextab.*)
48    } >ROM
49
50    .ARM.exidx . : {
51        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
52    } >ROM
53
54    .rodata . : {
55        __RODATA_START__ = .;
56
57        *(SORT_BY_ALIGNMENT(.rodata*))
58
59        RODATA_COMMON
60
61        /*
62         * No need to pad out the .rodata section to a page boundary. Next is
63         * the .data section, which can mapped in ROM with the same memory
64         * attributes as the .rodata section.
65         *
66         * Pad out to 16 bytes though as .data section needs to be 16-byte
67         * aligned and lld does not align the LMA to the alignment specified
68         * on the .data section.
69         */
70        __RODATA_END__ = .;
71
72        . = ALIGN(16);
73    } >ROM
74#else /* SEPARATE_CODE_AND_RODATA */
75    .ro . : {
76        __RO_START__ = .;
77
78        *bl1_entrypoint.o(.text*)
79        *(SORT_BY_ALIGNMENT(.text*))
80        *(SORT_BY_ALIGNMENT(.rodata*))
81
82        RODATA_COMMON
83
84        *(.vectors)
85
86        __RO_END__ = .;
87
88        /*
89         * Pad out to 16 bytes as the .data section needs to be 16-byte aligned
90         * and lld does not align the LMA to the alignment specified on the
91         * .data section.
92         */
93        . = ALIGN(16);
94    } >ROM
95#endif /* SEPARATE_CODE_AND_RODATA */
96
97    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
98        "cpu_ops not defined for this platform.")
99
100    . = BL1_RW_BASE;
101
102    ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
103        "BL1_RW_BASE address is not aligned on a page boundary.")
104
105    DATA_SECTION >RAM AT>ROM
106
107    __DATA_RAM_START__ = __DATA_START__;
108    __DATA_RAM_END__ = __DATA_END__;
109
110    STACK_SECTION >RAM
111    BSS_SECTION >RAM
112    XLAT_TABLE_SECTION >RAM
113
114#if USE_COHERENT_MEM
115    /*
116     * The base address of the coherent memory section must be page-aligned to
117     * guarantee that the coherent data are stored on their own pages and are
118     * not mixed with normal data. This is required to set up the correct memory
119     * attributes for the coherent data page tables.
120     */
121    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
122        __COHERENT_RAM_START__ = .;
123        *(.tzfw_coherent_mem)
124        __COHERENT_RAM_END_UNALIGNED__ = .;
125
126        /*
127         * Memory page(s) mapped to this section will be marked as device
128         * memory. No other unexpected data must creep in. Ensure the rest of
129         * the current memory page is unused.
130         */
131        . = ALIGN(PAGE_SIZE);
132
133        __COHERENT_RAM_END__ = .;
134    } >RAM
135#endif /* USE_COHERENT_MEM */
136
137    __BL1_RAM_START__ = ADDR(.data);
138    __BL1_RAM_END__ = .;
139
140    __DATA_ROM_START__ = LOADADDR(.data);
141    __DATA_SIZE__ = SIZEOF(.data);
142
143    /*
144     * The .data section is the last PROGBITS section so its end marks the end
145     * of BL1's actual content in Trusted ROM.
146     */
147    __BL1_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
148
149    ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
150        "BL1's ROM content has exceeded its limit.")
151
152    __BSS_SIZE__ = SIZEOF(.bss);
153
154#if USE_COHERENT_MEM
155    __COHERENT_RAM_UNALIGNED_SIZE__ =
156        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
157#endif /* USE_COHERENT_MEM */
158
159    ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
160}
161