1/*
2 * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <context.h>
11#include <el3_common_macros.S>
12#include <smccc_helpers.h>
13#include <smccc_macros.S>
14
15	.globl	bl1_vector_table
16	.globl	bl1_entrypoint
17
18	/* -----------------------------------------------------
19	 * Setup the vector table to support SVC & MON mode.
20	 * -----------------------------------------------------
21	 */
22vector_base bl1_vector_table
23	b	bl1_entrypoint
24	b	report_exception	/* Undef */
25	b	bl1_aarch32_smc_handler	/* SMC call */
26	b	report_prefetch_abort	/* Prefetch abort */
27	b	report_data_abort	/* Data abort */
28	b	report_exception	/* Reserved */
29	b	report_exception	/* IRQ */
30	b	report_exception	/* FIQ */
31
32	/* -----------------------------------------------------
33	 * bl1_entrypoint() is the entry point into the trusted
34	 * firmware code when a cpu is released from warm or
35	 * cold reset.
36	 * -----------------------------------------------------
37	 */
38
39func bl1_entrypoint
40/* ---------------------------------------------------------------------
41* If the reset address is programmable then bl1_entrypoint() is
42* executed only on the cold boot path. Therefore, we can skip the warm
43* boot mailbox mechanism.
44* ---------------------------------------------------------------------
45*/
46	el3_entrypoint_common					\
47		_init_sctlr=1					\
48		_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS	\
49		_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU	\
50		_init_memory=1					\
51		_init_c_runtime=1				\
52		_exception_vectors=bl1_vector_table		\
53		_pie_fixup_size=0
54
55	/* -----------------------------------------------------
56	 * Perform BL1 setup
57	 * -----------------------------------------------------
58	 */
59	bl	bl1_setup
60
61	/* -----------------------------------------------------
62	 * Jump to main function.
63	 * -----------------------------------------------------
64	 */
65	bl	bl1_main
66
67	/* -----------------------------------------------------
68	 * Jump to next image.
69	 * -----------------------------------------------------
70	 */
71
72	/*
73	 * Get the smc_context for next BL image,
74	 * program the gp/system registers and save it in `r4`.
75	 */
76	bl	smc_get_next_ctx
77	mov	r4, r0
78
79	/* Only turn-off MMU if going to secure world */
80	ldr	r5, [r4, #SMC_CTX_SCR]
81	tst	r5, #SCR_NS_BIT
82	bne	skip_mmu_off
83
84	/*
85	 * MMU needs to be disabled because both BL1 and BL2/BL2U execute
86	 * in PL1, and therefore share the same address space.
87	 * BL2/BL2U will initialize the address space according to its
88	 * own requirement.
89	 */
90	bl	disable_mmu_icache_secure
91	stcopr	r0, TLBIALL
92	dsb	sy
93	isb
94
95skip_mmu_off:
96	/* Restore smc_context from `r4` and exit secure monitor mode. */
97	mov	r0, r4
98	monitor_exit
99endfunc bl1_entrypoint
100