1 /*
2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/arm/gicv2.h>
13 #include <lib/mmio.h>
14 #include <lib/psci/psci.h>
15 #include <plat/arm/common/plat_arm.h>
16 #include <plat/common/platform.h>
17
18 #include <plat_private.h>
19 #include "pm_api_sys.h"
20 #include "pm_client.h"
21
22 static uintptr_t zynqmp_sec_entry;
23
zynqmp_cpu_standby(plat_local_state_t cpu_state)24 static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
25 {
26 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
27
28 dsb();
29 wfi();
30 }
31
zynqmp_pwr_domain_on(u_register_t mpidr)32 static int32_t zynqmp_pwr_domain_on(u_register_t mpidr)
33 {
34 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
35 const struct pm_proc *proc;
36 uint32_t buff[3];
37 enum pm_ret_status ret;
38
39 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
40
41 if (cpu_id == -1) {
42 return PSCI_E_INTERN_FAIL;
43 }
44 proc = pm_get_proc(cpu_id);
45
46 /* Check the APU proc status before wakeup */
47 ret = pm_get_node_status(proc->node_id, buff);
48 if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) {
49 return PSCI_E_INTERN_FAIL;
50 }
51
52 /* Clear power down request */
53 pm_client_wakeup(proc);
54
55 /* Send request to PMU to wake up selected APU CPU core */
56 pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING);
57
58 return PSCI_E_SUCCESS;
59 }
60
zynqmp_pwr_domain_off(const psci_power_state_t * target_state)61 static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
62 {
63 uint32_t cpu_id = plat_my_core_pos();
64 const struct pm_proc *proc = pm_get_proc(cpu_id);
65
66 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
67 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
68 __func__, i, target_state->pwr_domain_state[i]);
69 }
70
71 /* Prevent interrupts from spuriously waking up this cpu */
72 gicv2_cpuif_disable();
73
74 /*
75 * Send request to PMU to power down the appropriate APU CPU
76 * core.
77 * According to PSCI specification, CPU_off function does not
78 * have resume address and CPU core can only be woken up
79 * invoking CPU_on function, during which resume address will
80 * be set.
81 */
82 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
83 }
84
zynqmp_pwr_domain_suspend(const psci_power_state_t * target_state)85 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
86 {
87 uint32_t state;
88 uint32_t cpu_id = plat_my_core_pos();
89 const struct pm_proc *proc = pm_get_proc(cpu_id);
90
91 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
92 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
93 __func__, i, target_state->pwr_domain_state[i]);
94
95 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
96 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
97
98 /* Send request to PMU to suspend this core */
99 pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry);
100
101 /* APU is to be turned off */
102 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
103 /* disable coherency */
104 plat_arm_interconnect_exit_coherency();
105 }
106 }
107
zynqmp_pwr_domain_on_finish(const psci_power_state_t * target_state)108 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
109 {
110 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
111 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
112 __func__, i, target_state->pwr_domain_state[i]);
113 }
114 plat_arm_gic_pcpu_init();
115 gicv2_cpuif_enable();
116 }
117
zynqmp_pwr_domain_suspend_finish(const psci_power_state_t * target_state)118 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
119 {
120 uint32_t cpu_id = plat_my_core_pos();
121 const struct pm_proc *proc = pm_get_proc(cpu_id);
122
123 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
124 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
125 __func__, i, target_state->pwr_domain_state[i]);
126 }
127
128 /* Clear the APU power control register for this cpu */
129 pm_client_wakeup(proc);
130
131 /* enable coherency */
132 plat_arm_interconnect_enter_coherency();
133 /* APU was turned off */
134 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
135 plat_arm_gic_init();
136 } else {
137 gicv2_cpuif_enable();
138 gicv2_pcpu_distif_init();
139 }
140 }
141
142 /*******************************************************************************
143 * ZynqMP handlers to shutdown/reboot the system
144 ******************************************************************************/
145
zynqmp_system_off(void)146 static void __dead2 zynqmp_system_off(void)
147 {
148 /* disable coherency */
149 plat_arm_interconnect_exit_coherency();
150
151 /* Send the power down request to the PMU */
152 pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN,
153 pm_get_shutdown_scope());
154
155 while (1) {
156 wfi();
157 }
158 }
159
zynqmp_system_reset(void)160 static void __dead2 zynqmp_system_reset(void)
161 {
162 /* disable coherency */
163 plat_arm_interconnect_exit_coherency();
164
165 /* Send the system reset request to the PMU */
166 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
167 pm_get_shutdown_scope());
168
169 while (1) {
170 wfi();
171 }
172 }
173
zynqmp_validate_power_state(uint32_t power_state,psci_power_state_t * req_state)174 static int32_t zynqmp_validate_power_state(uint32_t power_state,
175 psci_power_state_t *req_state)
176 {
177 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
178
179 uint32_t pstate = psci_get_pstate_type(power_state);
180
181 assert(req_state);
182
183 /* Sanity check the requested state */
184 if (pstate == PSTATE_TYPE_STANDBY) {
185 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
186 } else {
187 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
188 }
189 /* We expect the 'state id' to be zero */
190 if (psci_get_pstate_id(power_state)) {
191 return PSCI_E_INVALID_PARAMS;
192 }
193
194 return PSCI_E_SUCCESS;
195 }
196
zynqmp_get_sys_suspend_power_state(psci_power_state_t * req_state)197 static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state)
198 {
199 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
200 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
201 }
202
203 /*******************************************************************************
204 * Export the platform handlers to enable psci to invoke them
205 ******************************************************************************/
206 static const struct plat_psci_ops zynqmp_psci_ops = {
207 .cpu_standby = zynqmp_cpu_standby,
208 .pwr_domain_on = zynqmp_pwr_domain_on,
209 .pwr_domain_off = zynqmp_pwr_domain_off,
210 .pwr_domain_suspend = zynqmp_pwr_domain_suspend,
211 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish,
212 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish,
213 .system_off = zynqmp_system_off,
214 .system_reset = zynqmp_system_reset,
215 .validate_power_state = zynqmp_validate_power_state,
216 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
217 };
218
219 /*******************************************************************************
220 * Export the platform specific power ops.
221 ******************************************************************************/
plat_setup_psci_ops(uintptr_t sec_entrypoint,const struct plat_psci_ops ** psci_ops)222 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
223 const struct plat_psci_ops **psci_ops)
224 {
225 zynqmp_sec_entry = sec_entrypoint;
226
227 *psci_ops = &zynqmp_psci_ops;
228
229 return 0;
230 }
231
