1 /*
2 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <platform_def.h>
11
12 #include <common/debug.h>
13 #include <drivers/delay_timer.h>
14 #include <drivers/gpio.h>
15 #include <lib/mmio.h>
16 #include <plat/common/platform.h>
17
18 #include <plat_private.h>
19 #include <soc.h>
20
21 struct gpio_save {
22 uint32_t swporta_dr;
23 uint32_t swporta_ddr;
24 uint32_t inten;
25 uint32_t intmask;
26 uint32_t inttype_level;
27 uint32_t int_polarity;
28 uint32_t debounce;
29 uint32_t ls_sync;
30 } store_gpio[3];
31
32 static uint32_t store_grf_gpio[(GRF_GPIO2D_HE - GRF_GPIO2A_IOMUX) / 4 + 1];
33
34 #define SWPORTA_DR 0x00
35 #define SWPORTA_DDR 0x04
36 #define INTEN 0x30
37 #define INTMASK 0x34
38 #define INTTYPE_LEVEL 0x38
39 #define INT_POLARITY 0x3c
40 #define DEBOUNCE 0x48
41 #define LS_SYNC 0x60
42
43 #define EXT_PORTA 0x50
44 #define PMU_GPIO_PORT0 0
45 #define PMU_GPIO_PORT1 1
46 #define GPIO_PORT2 2
47 #define GPIO_PORT3 3
48 #define GPIO_PORT4 4
49
50 #define PMU_GRF_GPIO0A_P 0x40
51 #define GRF_GPIO2A_P 0xe040
52 #define GPIO_P_MASK 0x03
53
54 #define GET_GPIO_PORT(pin) (pin / 32)
55 #define GET_GPIO_NUM(pin) (pin % 32)
56 #define GET_GPIO_BANK(pin) ((pin % 32) / 8)
57 #define GET_GPIO_ID(pin) ((pin % 32) % 8)
58
59 enum {
60 ENC_ZDZU,
61 ENC_ZUDR,
62 ENC_ZUDZ,
63 NUM_ENC
64 };
65
66 static const struct port_info {
67 uint32_t clkgate_reg;
68 uint32_t pull_base;
69 uint32_t port_base;
70 /*
71 * Selects the pull mode encoding per bank,
72 * first index for pull_type_{hw2sw,sw2hw}
73 */
74 uint8_t pull_enc[4];
75 uint8_t clkgate_bit;
76 uint8_t max_bank;
77 } port_info[] = {
78 {
79 .clkgate_reg = PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
80 .pull_base = PMUGRF_BASE + PMUGRF_GPIO0A_P,
81 .port_base = GPIO0_BASE,
82 .pull_enc = {ENC_ZDZU, ENC_ZDZU},
83 .clkgate_bit = PCLK_GPIO0_GATE_SHIFT,
84 .max_bank = 1,
85 }, {
86 .clkgate_reg = PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
87 .pull_base = PMUGRF_BASE + PMUGRF_GPIO1A_P,
88 .port_base = GPIO1_BASE,
89 .pull_enc = {ENC_ZUDR, ENC_ZUDR, ENC_ZUDR, ENC_ZUDR},
90 .clkgate_bit = PCLK_GPIO1_GATE_SHIFT,
91 .max_bank = 3,
92 }, {
93 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
94 .pull_base = GRF_BASE + GRF_GPIO2A_P,
95 .port_base = GPIO2_BASE,
96 .pull_enc = {ENC_ZUDR, ENC_ZUDR, ENC_ZDZU, ENC_ZDZU},
97 .clkgate_bit = PCLK_GPIO2_GATE_SHIFT,
98 .max_bank = 3,
99 }, {
100 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
101 .pull_base = GRF_BASE + GRF_GPIO3A_P,
102 .port_base = GPIO3_BASE,
103 .pull_enc = {ENC_ZUDR, ENC_ZUDR, ENC_ZUDR, ENC_ZUDR},
104 .clkgate_bit = PCLK_GPIO3_GATE_SHIFT,
105 .max_bank = 3,
106 }, {
107 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
108 .pull_base = GRF_BASE + GRF_GPIO4A_P,
109 .port_base = GPIO4_BASE,
110 .pull_enc = {ENC_ZUDR, ENC_ZUDR, ENC_ZUDR, ENC_ZUDR},
111 .clkgate_bit = PCLK_GPIO4_GATE_SHIFT,
112 .max_bank = 3,
113 }
114 };
115
116 /*
117 * Mappings between TF-A constants and hardware encodings:
118 * there are 3 different encoding schemes that may differ between
119 * banks of the same port: the corresponding value of the pull_enc array
120 * in port_info is used as the first index
121 */
122 static const uint8_t pull_type_hw2sw[NUM_ENC][4] = {
123 [ENC_ZDZU] = {GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_NONE, GPIO_PULL_UP},
124 [ENC_ZUDR] = {GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN, GPIO_PULL_REPEATER},
125 [ENC_ZUDZ] = {GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN, GPIO_PULL_NONE}
126 };
127 static const uint8_t pull_type_sw2hw[NUM_ENC][4] = {
128 [ENC_ZDZU] = {
129 [GPIO_PULL_NONE] = 0,
130 [GPIO_PULL_DOWN] = 1,
131 [GPIO_PULL_UP] = 3,
132 [GPIO_PULL_REPEATER] = -1
133 },
134 [ENC_ZUDR] = {
135 [GPIO_PULL_NONE] = 0,
136 [GPIO_PULL_DOWN] = 2,
137 [GPIO_PULL_UP] = 1,
138 [GPIO_PULL_REPEATER] = 3
139 },
140 [ENC_ZUDZ] = {
141 [GPIO_PULL_NONE] = 0,
142 [GPIO_PULL_DOWN] = 2,
143 [GPIO_PULL_UP] = 1,
144 [GPIO_PULL_REPEATER] = -1
145 }
146 };
147
148 /* Return old clock state, enables clock, in order to do GPIO access */
gpio_get_clock(uint32_t gpio_number)149 static int gpio_get_clock(uint32_t gpio_number)
150 {
151 uint32_t port = GET_GPIO_PORT(gpio_number);
152 assert(port < 5U);
153
154 const struct port_info *info = &port_info[port];
155
156 if ((mmio_read_32(info->clkgate_reg) & (1U << info->clkgate_bit)) == 0U) {
157 return 0;
158 }
159 mmio_write_32(
160 info->clkgate_reg,
161 BITS_WITH_WMASK(0, 1, info->clkgate_bit)
162 );
163 return 1;
164 }
165
166 /* Restore old state of gpio clock, assuming it is running now */
gpio_put_clock(uint32_t gpio_number,uint32_t clock_state)167 void gpio_put_clock(uint32_t gpio_number, uint32_t clock_state)
168 {
169 if (clock_state == 0) {
170 return;
171 }
172 uint32_t port = GET_GPIO_PORT(gpio_number);
173 const struct port_info *info = &port_info[port];
174
175 mmio_write_32(info->clkgate_reg, BITS_WITH_WMASK(1, 1, info->clkgate_bit));
176 }
177
get_pull(int gpio)178 static int get_pull(int gpio)
179 {
180 uint32_t port = GET_GPIO_PORT(gpio);
181 uint32_t bank = GET_GPIO_BANK(gpio);
182 uint32_t id = GET_GPIO_ID(gpio);
183 uint32_t val, clock_state;
184
185 assert(port < 5U);
186 const struct port_info *info = &port_info[port];
187
188 assert(bank <= info->max_bank);
189
190 clock_state = gpio_get_clock(gpio);
191 val = (mmio_read_32(info->pull_base + 4 * bank) >> (id * 2)) & GPIO_P_MASK;
192 gpio_put_clock(gpio, clock_state);
193
194 return pull_type_hw2sw[info->pull_enc[bank]][val];
195 }
196
set_pull(int gpio,int pull)197 static void set_pull(int gpio, int pull)
198 {
199 uint32_t port = GET_GPIO_PORT(gpio);
200 uint32_t bank = GET_GPIO_BANK(gpio);
201 uint32_t id = GET_GPIO_ID(gpio);
202 uint32_t clock_state;
203
204 assert(port < 5U);
205 const struct port_info *info = &port_info[port];
206
207 assert(bank <= info->max_bank);
208
209 uint8_t val = pull_type_sw2hw[info->pull_enc[bank]][pull];
210
211 assert(val != (uint8_t)-1);
212
213 clock_state = gpio_get_clock(gpio);
214 mmio_write_32(
215 info->pull_base + 4 * bank,
216 BITS_WITH_WMASK(val, GPIO_P_MASK, id * 2)
217 );
218 gpio_put_clock(gpio, clock_state);
219 }
220
set_direction(int gpio,int direction)221 static void set_direction(int gpio, int direction)
222 {
223 uint32_t port = GET_GPIO_PORT(gpio);
224 uint32_t num = GET_GPIO_NUM(gpio);
225 uint32_t clock_state;
226
227 assert((port < 5) && (num < 32));
228
229 clock_state = gpio_get_clock(gpio);
230
231 /*
232 * in gpio.h
233 * #define GPIO_DIR_OUT 0
234 * #define GPIO_DIR_IN 1
235 * but rk3399 gpio direction 1: output, 0: input
236 * so need to revert direction value
237 */
238 mmio_setbits_32(
239 port_info[port].port_base + SWPORTA_DDR,
240 ((direction == 0) ? 1 : 0) << num
241 );
242 gpio_put_clock(gpio, clock_state);
243 }
244
get_direction(int gpio)245 static int get_direction(int gpio)
246 {
247 uint32_t port = GET_GPIO_PORT(gpio);
248 uint32_t num = GET_GPIO_NUM(gpio);
249 int direction, clock_state;
250
251 assert((port < 5U) && (num < 32U));
252
253 clock_state = gpio_get_clock(gpio);
254
255 /*
256 * in gpio.h
257 * #define GPIO_DIR_OUT 0
258 * #define GPIO_DIR_IN 1
259 * but rk3399 gpio direction 1: output, 0: input
260 * so need to revert direction value
261 */
262 direction = (((mmio_read_32(
263 port_info[port].port_base + SWPORTA_DDR
264 ) >> num) & 1U) == 0) ? 1 : 0;
265 gpio_put_clock(gpio, clock_state);
266
267 return direction;
268 }
269
get_value(int gpio)270 static int get_value(int gpio)
271 {
272 uint32_t port = GET_GPIO_PORT(gpio);
273 uint32_t num = GET_GPIO_NUM(gpio);
274 int value, clock_state;
275
276 assert((port < 5) && (num < 32));
277
278 clock_state = gpio_get_clock(gpio);
279 value = (mmio_read_32(port_info[port].port_base + EXT_PORTA) >> num) &
280 0x1U;
281 gpio_put_clock(gpio, clock_state);
282
283 return value;
284 }
285
set_value(int gpio,int value)286 static void set_value(int gpio, int value)
287 {
288 uint32_t port = GET_GPIO_PORT(gpio);
289 uint32_t num = GET_GPIO_NUM(gpio);
290 uint32_t clock_state;
291
292 assert((port < 5U) && (num < 32U));
293
294 clock_state = gpio_get_clock(gpio);
295 mmio_clrsetbits_32(
296 port_info[port].port_base + SWPORTA_DR,
297 1 << num,
298 ((value == 0) ? 0 : 1) << num
299 );
300 gpio_put_clock(gpio, clock_state);
301 }
302
plat_rockchip_save_gpio(void)303 void plat_rockchip_save_gpio(void)
304 {
305 unsigned int i;
306 uint32_t cru_gate_save;
307
308 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31));
309
310 /*
311 * when shutdown logic, we need to save gpio2 ~ gpio4 register,
312 * we need to enable gpio2 ~ gpio4 clock here, since it may be gating,
313 * and we do not care gpio0 and gpio1 clock gate, since we never
314 * gating them
315 */
316 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
317 BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
318
319 /*
320 * since gpio0, gpio1 are pmugpio, they will keep ther value
321 * when shutdown logic power rail, so only need to save gpio2 ~ gpio4
322 * register value
323 */
324 for (i = 2; i < 5; i++) {
325 uint32_t base = port_info[i].port_base;
326
327 store_gpio[i - 2] = (struct gpio_save) {
328 .swporta_dr = mmio_read_32(base + SWPORTA_DR),
329 .swporta_ddr = mmio_read_32(base + SWPORTA_DDR),
330 .inten = mmio_read_32(base + INTEN),
331 .intmask = mmio_read_32(base + INTMASK),
332 .inttype_level = mmio_read_32(base + INTTYPE_LEVEL),
333 .int_polarity = mmio_read_32(base + INT_POLARITY),
334 .debounce = mmio_read_32(base + DEBOUNCE),
335 .ls_sync = mmio_read_32(base + LS_SYNC),
336 };
337 }
338 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
339 cru_gate_save | REG_SOC_WMSK);
340
341 /*
342 * gpio0, gpio1 in pmuiomux, they will keep ther value
343 * when shutdown logic power rail, so only need to save gpio2 ~ gpio4
344 * iomux register value
345 */
346 for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++)
347 store_grf_gpio[i] =
348 mmio_read_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4);
349 }
350
plat_rockchip_restore_gpio(void)351 void plat_rockchip_restore_gpio(void)
352 {
353 int i;
354 uint32_t cru_gate_save;
355
356 for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++)
357 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,
358 REG_SOC_WMSK | store_grf_gpio[i]);
359
360 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31));
361
362 /*
363 * when shutdown logic, we need to save gpio2 ~ gpio4 register,
364 * we need to enable gpio2 ~ gpio4 clock here, since it may be gating,
365 * and we do not care gpio0 and gpio1 clock gate, since we never
366 * gating them
367 */
368 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
369 BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
370
371 for (i = 2; i < 5; i++) {
372 uint32_t base = port_info[i].port_base;
373 const struct gpio_save *save = &store_gpio[i - 2];
374
375 mmio_write_32(base + SWPORTA_DR, save->swporta_dr);
376 mmio_write_32(base + SWPORTA_DDR, save->swporta_ddr);
377 mmio_write_32(base + INTEN, save->inten);
378 mmio_write_32(base + INTMASK, save->intmask);
379 mmio_write_32(base + INTTYPE_LEVEL, save->inttype_level),
380 mmio_write_32(base + INT_POLARITY, save->int_polarity);
381 mmio_write_32(base + DEBOUNCE, save->debounce);
382 mmio_write_32(base + LS_SYNC, save->ls_sync);
383 }
384 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
385 cru_gate_save | REG_SOC_WMSK);
386 }
387
388 const gpio_ops_t rk3399_gpio_ops = {
389 .get_direction = get_direction,
390 .set_direction = set_direction,
391 .get_value = get_value,
392 .set_value = set_value,
393 .set_pull = set_pull,
394 .get_pull = get_pull,
395 };
396
plat_rockchip_gpio_init(void)397 void plat_rockchip_gpio_init(void)
398 {
399 gpio_init(&rk3399_gpio_ops);
400 }
401
