1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <string.h>
8
9 #include <common/debug.h>
10 #include <lib/mmio.h>
11
12 #include <mt_spm.h>
13 #include <mt_spm_internal.h>
14 #include <mt_spm_pmic_wrap.h>
15 #include <mt_spm_reg.h>
16 #include <plat_pm.h>
17 #include <platform_def.h>
18
19 /* PMIC_WRAP MT6359 */
20 #define VCORE_BASE_UV 40000
21 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
22 #define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
23
24 #define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
25 #define SPM_DATA_SHIFT 16
26
27 #define BUCK_VGPU11_ELR0 0x15B4
28 #define TOP_SPI_CON0 0x0456
29 #define BUCK_TOP_CON1 0x1443
30 #define TOP_CON 0x0013
31 #define TOP_DIG_WPK 0x03a9
32 #define TOP_CON_LOCK 0x03a8
33 #define TOP_CLK_CON0 0x0134
34
35 struct pmic_wrap_cmd {
36 unsigned long cmd_addr;
37 unsigned long cmd_wdata;
38 };
39
40 struct pmic_wrap_setting {
41 enum pmic_wrap_phase_id phase;
42 struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
43 struct {
44 struct {
45 unsigned long cmd_addr;
46 unsigned long cmd_wdata;
47 } _[NR_PMIC_WRAP_CMD];
48 const int nr_idx;
49 } set[NR_PMIC_WRAP_PHASE];
50 };
51
52 static struct pmic_wrap_setting pw = {
53 .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
54 .addr = { {0UL, 0UL} },
55 .set[PMIC_WRAP_PHASE_ALLINONE] = {
56 ._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(75000),},
57 ._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
58 ._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
59 ._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(55000),},
60 ._[CMD_4] = {TOP_SPI_CON0, 0x1,},
61 ._[CMD_5] = {TOP_SPI_CON0, 0x0,},
62 ._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
63 ._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
64 ._[CMD_8] = {TOP_CON, 0x3,},
65 ._[CMD_9] = {TOP_CON, 0x0,},
66 ._[CMD_10] = {TOP_DIG_WPK, 0x63,},
67 ._[CMD_11] = {TOP_CON_LOCK, 0x15,},
68 ._[CMD_12] = {TOP_DIG_WPK, 0x0,},
69 ._[CMD_13] = {TOP_CON_LOCK, 0x0,},
70 ._[CMD_14] = {TOP_CLK_CON0, 0x40,},
71 ._[CMD_15] = {TOP_CLK_CON0, 0x0,},
72 .nr_idx = NR_IDX_ALL,
73 },
74 };
75
_mt_spm_pmic_table_init(void)76 void _mt_spm_pmic_table_init(void)
77 {
78 struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
79 {(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
80 {(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
81 {(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
82 {(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
83 {(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
84 {(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
85 {(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
86 {(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
87 {(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
88 {(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
89 {(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
90 {(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
91 {(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
92 {(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
93 {(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
94 {(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
95 };
96
97 memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
98 }
99
mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)100 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
101 {
102 uint32_t idx, addr, data;
103
104 if (phase >= NR_PMIC_WRAP_PHASE) {
105 return;
106 }
107
108 if (pw.phase == phase) {
109 return;
110 }
111
112 if (pw.addr[0].cmd_addr == 0UL) {
113 _mt_spm_pmic_table_init();
114 }
115
116 pw.phase = phase;
117 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
118
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
121 data = pw.set[phase]._[idx].cmd_wdata;
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
123 }
124 }
125
mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,uint32_t idx,uint32_t cmd_wdata)126 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
127 uint32_t cmd_wdata)
128 {
129 uint32_t addr;
130
131 if (phase >= NR_PMIC_WRAP_PHASE) {
132 return;
133 }
134
135 if (idx >= pw.set[phase].nr_idx) {
136 return;
137 }
138
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
140 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
141
142 if (pw.phase == phase) {
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
145 }
146 }
147
mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,uint32_t idx)148 uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
149 {
150 if (phase >= NR_PMIC_WRAP_PHASE) {
151 return 0UL;
152 }
153
154 if (idx >= pw.set[phase].nr_idx) {
155 return 0UL;
156 }
157
158 return pw.set[phase]._[idx].cmd_wdata;
159 }
160
