1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9
10 #include <mt_lp_rm.h>
11 #include <mt_spm.h>
12 #include <mt_spm_cond.h>
13 #include <mt_spm_constraint.h>
14 #include <mt_spm_conservation.h>
15 #include <mt_spm_idle.h>
16 #include <mt_spm_internal.h>
17 #include <mt_spm_notifier.h>
18 #include <mt_spm_rc_internal.h>
19 #include <mt_spm_resource_req.h>
20 #include <mt_spm_reg.h>
21 #include <mt_spm_suspend.h>
22 #include <plat_pm.h>
23 #include <plat_mtk_lpm.h>
24
25 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
26 #include <mt_gic_v3.h>
27 #include <mtk_cirq.h>
28 #endif
29
30 #define CONSTRAINT_BUS26M_ALLOW \
31 (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
32 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
33 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
34 MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
35 MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
36 MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
37
38 #define CONSTRAINT_BUS26M_PCM_FLAG \
39 (SPM_FLAG_DISABLE_INFRA_PDN | \
40 SPM_FLAG_DISABLE_VCORE_DVS | \
41 SPM_FLAG_DISABLE_VCORE_DFS | \
42 SPM_FLAG_SRAM_SLEEP_CTRL | \
43 SPM_FLAG_ENABLE_TIA_WORKAROUND | \
44 SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
45 SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
46 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
47
48 #define CONSTRAINT_BUS26M_PCM_FLAG1 0U
49
50 #define CONSTRAINT_BUS26M_RESOURCE_REQ 0U
51
52 static unsigned int bus26m_ext_opand;
53 static struct mt_irqremain *refer2remain_irq;
54 static struct mt_spm_cond_tables cond_bus26m = {
55 .name = "bus26m",
56 .table_cg = {
57 0xFFFFD408, /* MTCMOS1 */
58 0x2284C802, /* INFRA0 */
59 0x27AF8000, /* INFRA1 */
60 0x86040650, /* INFRA2 */
61 0x30038020, /* INFRA3 */
62 0x80000000, /* INFRA4 */
63 0x00080ABB, /* PERI0 */
64 0x00004000, /* VPPSYS0_0 */
65 0x08803000, /* VPPSYS0_1 */
66 0x00000000, /* VPPSYS0_2 */
67 0x80005555, /* VPPSYS1_0 */
68 0x00009008, /* VPPSYS1_1 */
69 0x60060000, /* VDOSYS0_0 */
70 0x00000000, /* VDOSYS0_1 */
71 0x201E01F8, /* VDOSYS1_0 */
72 0x00800000, /* VDOSYS1_1 */
73 0x00000000, /* VDOSYS1_2 */
74 0x00000080, /* I2C */
75 },
76 .table_pll = (PLL_BIT_UNIVPLL |
77 PLL_BIT_MFGPLL |
78 PLL_BIT_MSDCPLL |
79 PLL_BIT_TVDPLL |
80 PLL_BIT_MMPLL),
81 };
82
83 static struct mt_spm_cond_tables cond_bus26m_res = {
84 .table_cg = { 0U },
85 .table_pll = 0U,
86 };
87
88 static struct constraint_status status = {
89 .id = MT_RM_CONSTRAINT_ID_BUS26M,
90 .valid = (MT_SPM_RC_VALID_SW |
91 MT_SPM_RC_VALID_COND_LATCH),
92 .cond_block = 0U,
93 .enter_cnt = 0U,
94 .cond_res = &cond_bus26m_res,
95 };
96
97 /*
98 * Cirq will take the place of gic when gic is off.
99 * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
100 * Therefore, we need to set irq pending for specific wakeup source.
101 */
102 #ifdef ATF_PLAT_CIRQ_UNSUPPORT
103 #define do_irqs_delivery()
104 #else
mt_spm_irq_remain_dump(struct mt_irqremain * irqs,unsigned int irq_index,struct wake_status * wakeup)105 static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
106 unsigned int irq_index,
107 struct wake_status *wakeup)
108 {
109 INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
110 wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
111 wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
112 wakeup->tr.comm.b_sw_flag1);
113
114 INFO("irq:%u(0x%08x) set pending\n",
115 irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
116 }
117
do_irqs_delivery(void)118 static void do_irqs_delivery(void)
119 {
120 unsigned int idx;
121 int res = 0;
122 struct wake_status *wakeup = NULL;
123 struct mt_irqremain *irqs = refer2remain_irq;
124
125 res = spm_conservation_get_result(&wakeup);
126
127 if ((res != 0) && (irqs == NULL)) {
128 return;
129 }
130
131 for (idx = 0U; idx < irqs->count; ++idx) {
132 if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
133 ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
134 if ((irqs->wakeupsrc_cat[idx] &
135 MT_IRQ_REMAIN_CAT_LOG) != 0U) {
136 mt_spm_irq_remain_dump(irqs, idx, wakeup);
137 }
138
139 mt_irq_set_pending(irqs->irqs[idx]);
140 }
141 }
142 }
143 #endif
144
spm_bus26m_conduct(struct spm_lp_scen * spm_lp,unsigned int * resource_req)145 static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp,
146 unsigned int *resource_req)
147 {
148 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
149 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
150 *resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
151 }
152
spm_is_valid_rc_bus26m(unsigned int cpu,int state_id)153 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
154 {
155 (void)cpu;
156 (void)state_id;
157
158 return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
159 }
160
spm_update_rc_bus26m(int state_id,int type,const void * val)161 int spm_update_rc_bus26m(int state_id, int type, const void *val)
162 {
163 const struct mt_spm_cond_tables *tlb;
164 const struct mt_spm_cond_tables *tlb_check;
165 int res = MT_RM_STATUS_OK;
166
167 if (val == NULL) {
168 return MT_RM_STATUS_BAD;
169 }
170
171 if (type == PLAT_RC_UPDATE_CONDITION) {
172 tlb = (const struct mt_spm_cond_tables *)val;
173 tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
174
175 status.cond_block =
176 mt_spm_cond_check(state_id, tlb, tlb_check,
177 ((status.valid &
178 MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
179 &cond_bus26m_res : NULL);
180 } else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
181 refer2remain_irq = (struct mt_irqremain *)val;
182 } else {
183 res = MT_RM_STATUS_BAD;
184 }
185
186 return res;
187 }
188
spm_allow_rc_bus26m(int state_id)189 unsigned int spm_allow_rc_bus26m(int state_id)
190 {
191 (void)state_id;
192
193 return CONSTRAINT_BUS26M_ALLOW;
194 }
195
spm_run_rc_bus26m(unsigned int cpu,int state_id)196 int spm_run_rc_bus26m(unsigned int cpu, int state_id)
197 {
198 (void)cpu;
199
200 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
201 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
202 (IS_PLAT_SUSPEND_ID(state_id) ?
203 MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
204 #endif
205 if (IS_PLAT_SUSPEND_ID(state_id)) {
206 mt_spm_suspend_enter(state_id,
207 (MT_SPM_EX_OP_SET_WDT |
208 MT_SPM_EX_OP_HW_S1_DETECT |
209 MT_SPM_EX_OP_SET_SUSPEND_MODE |
210 bus26m_ext_opand),
211 CONSTRAINT_BUS26M_RESOURCE_REQ);
212 } else {
213 mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT,
214 spm_bus26m_conduct);
215 }
216
217 return 0;
218 }
219
spm_reset_rc_bus26m(unsigned int cpu,int state_id)220 int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
221 {
222 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
223
224 (void)cpu;
225
226 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
227 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
228 #endif
229 if (IS_PLAT_SUSPEND_ID(state_id)) {
230 ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
231 mt_spm_suspend_resume(state_id, ext_op, NULL);
232 bus26m_ext_opand = 0U;
233 } else {
234 mt_spm_idle_generic_resume(state_id, ext_op, NULL);
235 status.enter_cnt++;
236 }
237
238 do_irqs_delivery();
239
240 return 0;
241 }
242
