1 /*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9 #include <mt_lp_rm.h>
10 #include <mt_spm.h>
11 #include <mt_spm_cond.h>
12 #include <mt_spm_conservation.h>
13 #include <mt_spm_constraint.h>
14 #include <mt_spm_idle.h>
15 #include <mt_spm_internal.h>
16 #include <mt_spm_notifier.h>
17 #include <mt_spm_rc_internal.h>
18 #include <mt_spm_reg.h>
19 #include <mt_spm_resource_req.h>
20 #include <mt_spm_suspend.h>
21 #include <plat_mtk_lpm.h>
22 #include <plat_pm.h>
23
24 #define CONSTRAINT_DRAM_ALLOW \
25 (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
26 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
27 MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
28
29 #define CONSTRAINT_DRAM_PCM_FLAG \
30 (SPM_FLAG_DISABLE_INFRA_PDN | \
31 SPM_FLAG_DISABLE_VCORE_DVS | \
32 SPM_FLAG_DISABLE_VCORE_DFS | \
33 SPM_FLAG_SRAM_SLEEP_CTRL | \
34 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
35
36 #define CONSTRAINT_DRAM_PCM_FLAG1 (0U)
37
38 #define CONSTRAINT_DRAM_RESOURCE_REQ \
39 (MT_SPM_SYSPLL | \
40 MT_SPM_INFRA | \
41 MT_SPM_26M)
42
43 static struct mt_spm_cond_tables cond_dram = {
44 .name = "dram",
45 .table_cg = {
46 0x0385E03C, /* MTCMOS1 */
47 0x003F0100, /* INFRA0 */
48 0x08040802, /* INFRA1 */
49 0x06015641, /* INFRA2 */
50 0x00000000, /* INFRA3 */
51 0x00000000, /* INFRA4 */
52 0x00000000, /* INFRA5 */
53 0x02300020, /* MMSYS0 */
54 0x00000000, /* MMSYS1 */
55 0x00000000, /* MMSYS2 */
56 0x00015111, /* MMSYS3 */
57 },
58 .table_pll = 0U,
59 };
60
61 static struct mt_spm_cond_tables cond_dram_res = {
62 .table_cg = {0U},
63 .table_pll = 0U,
64 };
65
66 static struct constraint_status status = {
67 .id = MT_RM_CONSTRAINT_ID_DRAM,
68 .valid = (MT_SPM_RC_VALID_SW |
69 MT_SPM_RC_VALID_COND_LATCH |
70 MT_SPM_RC_VALID_XSOC_BBLPM),
71 .cond_block = 0U,
72 .enter_cnt = 0U,
73 .cond_res = &cond_dram_res,
74 };
75
spm_dram_conduct(struct spm_lp_scen * spm_lp,unsigned int * resource_req)76 static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
77 unsigned int *resource_req)
78 {
79 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
80 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
81 *resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
82 }
83
spm_is_valid_rc_dram(unsigned int cpu,int state_id)84 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
85 {
86 (void)cpu;
87 (void)state_id;
88
89 return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
90 }
91
spm_update_rc_dram(int state_id,int type,const void * val)92 int spm_update_rc_dram(int state_id, int type, const void *val)
93 {
94 const struct mt_spm_cond_tables *tlb;
95 const struct mt_spm_cond_tables *tlb_check;
96 int res = MT_RM_STATUS_OK;
97
98 if (val == NULL) {
99 res = MT_RM_STATUS_BAD;
100 } else {
101 if (type == PLAT_RC_UPDATE_CONDITION) {
102 tlb = (const struct mt_spm_cond_tables *)val;
103 tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
104 status.cond_block =
105 mt_spm_cond_check(state_id, tlb, tlb_check,
106 ((status.valid &
107 MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
108 (&cond_dram_res) : (NULL));
109 } else {
110 res = MT_RM_STATUS_BAD;
111 }
112 }
113
114 return res;
115 }
116
spm_allow_rc_dram(int state_id)117 unsigned int spm_allow_rc_dram(int state_id)
118 {
119 (void)state_id;
120
121 return CONSTRAINT_DRAM_ALLOW;
122 }
123
spm_run_rc_dram(unsigned int cpu,int state_id)124 int spm_run_rc_dram(unsigned int cpu, int state_id)
125 {
126 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
127 unsigned int allows = CONSTRAINT_DRAM_ALLOW;
128
129 (void)cpu;
130
131 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
132 #ifdef MT_SPM_USING_SRCLKEN_RC
133 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
134 #else
135 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
136 #endif
137 }
138
139 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
140 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
141 (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
142 #else
143 (void)allows;
144 #endif
145
146 if (IS_PLAT_SUSPEND_ID(state_id)) {
147 mt_spm_suspend_enter(state_id,
148 (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
149 CONSTRAINT_DRAM_RESOURCE_REQ);
150 } else {
151 mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
152 }
153
154 return 0;
155 }
156
spm_reset_rc_dram(unsigned int cpu,int state_id)157 int spm_reset_rc_dram(unsigned int cpu, int state_id)
158 {
159 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
160 unsigned int allows = CONSTRAINT_DRAM_ALLOW;
161
162 (void)cpu;
163
164 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
165 #ifdef MT_SPM_USING_SRCLKEN_RC
166 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
167 #else
168 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
169 #endif
170 }
171
172 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
173 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
174 #else
175 (void)allows;
176 #endif
177 if (IS_PLAT_SUSPEND_ID(state_id)) {
178 mt_spm_suspend_resume(state_id,
179 (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
180 NULL);
181 } else {
182 mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
183 status.enter_cnt++;
184 }
185
186 return 0;
187 }
188
