1 /*
2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch.h>
9 #include <arch_helpers.h>
10 #include <assert.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <common/desc_image_load.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <drivers/synopsys/dw_mmc.h>
16 #include <drivers/ti/uart/uart_16550.h>
17 #include <lib/xlat_tables/xlat_tables.h>
18
19 #include "agilex_mmc.h"
20 #include "agilex_clock_manager.h"
21 #include "agilex_memory_controller.h"
22 #include "agilex_pinmux.h"
23 #include "ccu/ncore_ccu.h"
24 #include "qspi/cadence_qspi.h"
25 #include "socfpga_emac.h"
26 #include "socfpga_f2sdram_manager.h"
27 #include "socfpga_handoff.h"
28 #include "socfpga_mailbox.h"
29 #include "socfpga_private.h"
30 #include "socfpga_reset_manager.h"
31 #include "socfpga_system_manager.h"
32 #include "wdt/watchdog.h"
33
34 static struct mmc_device_info mmc_info;
35
36 const mmap_region_t agilex_plat_mmap[] = {
37 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
38 MT_MEMORY | MT_RW | MT_NS),
39 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
40 MT_DEVICE | MT_RW | MT_NS),
41 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
42 MT_DEVICE | MT_RW | MT_SECURE),
43 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
44 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
45 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
46 MT_DEVICE | MT_RW | MT_SECURE),
47 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
48 MT_DEVICE | MT_RW | MT_NS),
49 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
50 MT_DEVICE | MT_RW | MT_NS),
51 {0},
52 };
53
54 boot_source_type boot_source = BOOT_SOURCE;
55
bl2_el3_early_platform_setup(u_register_t x0,u_register_t x1,u_register_t x2,u_register_t x4)56 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
57 u_register_t x2, u_register_t x4)
58 {
59 static console_t console;
60 handoff reverse_handoff_ptr;
61
62 generic_delay_timer_init();
63
64 if (socfpga_get_handoff(&reverse_handoff_ptr))
65 return;
66 config_pinmux(&reverse_handoff_ptr);
67 config_clkmgr_handoff(&reverse_handoff_ptr);
68
69 enable_nonsecure_access();
70 deassert_peripheral_reset();
71 config_hps_hs_before_warm_reset();
72
73 watchdog_init(get_wdt_clk());
74
75 console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(),
76 PLAT_BAUDRATE, &console);
77
78 socfpga_delay_timer_init();
79 init_ncore_ccu();
80 socfpga_emac_init();
81 init_hard_memory_controller();
82 mailbox_init();
83 agx_mmc_init();
84
85 if (!intel_mailbox_is_fpga_not_ready()) {
86 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
87 FPGA2SOC_MASK);
88 }
89 }
90
91
bl2_el3_plat_arch_setup(void)92 void bl2_el3_plat_arch_setup(void)
93 {
94
95 const mmap_region_t bl_regions[] = {
96 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
97 MT_MEMORY | MT_RW | MT_SECURE),
98 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
99 MT_CODE | MT_SECURE),
100 MAP_REGION_FLAT(BL_RO_DATA_BASE,
101 BL_RO_DATA_END - BL_RO_DATA_BASE,
102 MT_RO_DATA | MT_SECURE),
103 #if USE_COHERENT_MEM_BAR
104 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
105 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
106 MT_DEVICE | MT_RW | MT_SECURE),
107 #endif
108 {0},
109 };
110
111 setup_page_tables(bl_regions, agilex_plat_mmap);
112
113 enable_mmu_el3(0);
114
115 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
116
117 mmc_info.mmc_dev_type = MMC_IS_SD;
118 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
119
120 /* Request ownership and direct access to QSPI */
121 mailbox_hps_qspi_enable();
122
123 switch (boot_source) {
124 case BOOT_SOURCE_SDMMC:
125 dw_mmc_init(¶ms, &mmc_info);
126 socfpga_io_setup(boot_source);
127 break;
128
129 case BOOT_SOURCE_QSPI:
130 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
131 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
132 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
133 socfpga_io_setup(boot_source);
134 break;
135
136 default:
137 ERROR("Unsupported boot source\n");
138 panic();
139 break;
140 }
141 }
142
get_spsr_for_bl33_entry(void)143 uint32_t get_spsr_for_bl33_entry(void)
144 {
145 unsigned long el_status;
146 unsigned int mode;
147 uint32_t spsr;
148
149 /* Figure out what mode we enter the non-secure world in */
150 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
151 el_status &= ID_AA64PFR0_ELX_MASK;
152
153 mode = (el_status) ? MODE_EL2 : MODE_EL1;
154
155 /*
156 * TODO: Consider the possibility of specifying the SPSR in
157 * the FIP ToC and allowing the platform to have a say as
158 * well.
159 */
160 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
161 return spsr;
162 }
163
164
bl2_plat_handle_post_image_load(unsigned int image_id)165 int bl2_plat_handle_post_image_load(unsigned int image_id)
166 {
167 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
168
169 assert(bl_mem_params);
170
171 switch (image_id) {
172 case BL33_IMAGE_ID:
173 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
174 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
175 break;
176 default:
177 break;
178 }
179
180 return 0;
181 }
182
183 /*******************************************************************************
184 * Perform any BL3-1 platform setup code
185 ******************************************************************************/
bl2_platform_setup(void)186 void bl2_platform_setup(void)
187 {
188 }
189
190
