1 /*
2 * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <drivers/arm/gic600_multichip.h>
9 #include <plat/arm/common/plat_arm.h>
10 #include <plat/common/platform.h>
11 #include <sgi_soc_platform_def_v2.h>
12 #include <sgi_plat.h>
13
14 #if defined(IMAGE_BL31)
15 #if (CSS_SGI_PLATFORM_VARIANT == 2)
16 static const mmap_region_t rdn2mc_dynamic_mmap[] = {
17 #if CSS_SGI_CHIP_COUNT > 1
18 ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
19 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
20 #endif
21 #if CSS_SGI_CHIP_COUNT > 2
22 ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
23 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
24 #endif
25 #if CSS_SGI_CHIP_COUNT > 3
26 ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
27 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
28 #endif
29 };
30 #endif
31
32 #if (CSS_SGI_PLATFORM_VARIANT == 2)
33 static struct gic600_multichip_data rdn2mc_multichip_data __init = {
34 .rt_owner_base = PLAT_ARM_GICD_BASE,
35 .rt_owner = 0,
36 .chip_count = CSS_SGI_CHIP_COUNT,
37 .chip_addrs = {
38 PLAT_ARM_GICD_BASE >> 16,
39 #if CSS_SGI_CHIP_COUNT > 1
40 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
41 #endif
42 #if CSS_SGI_CHIP_COUNT > 2
43 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
44 #endif
45 #if CSS_SGI_CHIP_COUNT > 3
46 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
47 #endif
48 },
49 .spi_ids = {
50 {32, 479},
51 #if CSS_SGI_CHIP_COUNT > 1
52 {0, 0},
53 #endif
54 #if CSS_SGI_CHIP_COUNT > 2
55 {0, 0},
56 #endif
57 #if CSS_SGI_CHIP_COUNT > 3
58 {0, 0},
59 #endif
60 }
61 };
62 #endif
63
64 #if (CSS_SGI_PLATFORM_VARIANT == 2)
65 static uintptr_t rdn2mc_multichip_gicr_frames[] = {
66 /* Chip 0's GICR Base */
67 PLAT_ARM_GICR_BASE,
68 #if CSS_SGI_CHIP_COUNT > 1
69 /* Chip 1's GICR BASE */
70 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
71 #endif
72 #if CSS_SGI_CHIP_COUNT > 2
73 /* Chip 2's GICR BASE */
74 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
75 #endif
76 #if CSS_SGI_CHIP_COUNT > 3
77 /* Chip 3's GICR BASE */
78 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
79 #endif
80 UL(0) /* Zero Termination */
81 };
82 #endif
83 #endif /* IMAGE_BL31 */
84
plat_arm_sgi_get_platform_id(void)85 unsigned int plat_arm_sgi_get_platform_id(void)
86 {
87 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
88 & SID_SYSTEM_ID_PART_NUM_MASK;
89 }
90
plat_arm_sgi_get_config_id(void)91 unsigned int plat_arm_sgi_get_config_id(void)
92 {
93 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
94 }
95
plat_arm_sgi_get_multi_chip_mode(void)96 unsigned int plat_arm_sgi_get_multi_chip_mode(void)
97 {
98 return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
99 SID_MULTI_CHIP_MODE_MASK) >>
100 SID_MULTI_CHIP_MODE_SHIFT;
101 }
102
103 #if defined(IMAGE_BL31)
bl31_platform_setup(void)104 void bl31_platform_setup(void)
105 {
106 #if (CSS_SGI_PLATFORM_VARIANT == 2)
107 int ret;
108 unsigned int i;
109
110 if (plat_arm_sgi_get_multi_chip_mode() == 0) {
111 ERROR("Chip Count is set to %u but multi-chip mode is not "
112 "enabled\n", CSS_SGI_CHIP_COUNT);
113 panic();
114 } else {
115 INFO("Enabling multi-chip support for RD-N2 variant\n");
116
117 for (i = 0; i < ARRAY_SIZE(rdn2mc_dynamic_mmap); i++) {
118 ret = mmap_add_dynamic_region(
119 rdn2mc_dynamic_mmap[i].base_pa,
120 rdn2mc_dynamic_mmap[i].base_va,
121 rdn2mc_dynamic_mmap[i].size,
122 rdn2mc_dynamic_mmap[i].attr);
123 if (ret != 0) {
124 ERROR("Failed to add dynamic mmap entry for"
125 " i: %d " "(ret=%d)\n", i, ret);
126 panic();
127 }
128 }
129
130 plat_arm_override_gicr_frames(
131 rdn2mc_multichip_gicr_frames);
132 gic600_multichip_init(&rdn2mc_multichip_data);
133 }
134 #endif
135
136 sgi_bl31_common_platform_setup();
137 }
138 #endif /* IMAGE_BL31 */
139
