1 /*
2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /* Use the xlat_tables_v2 data structures: */
8 #define XLAT_TABLES_LIB_V2 1
9
10 #include <assert.h>
11
12 #include <bl1/bl1.h>
13 #include <common/tbbr/tbbr_img_def.h>
14 #include <drivers/arm/sp805.h>
15 #include <lib/fconf/fconf.h>
16 #include <lib/fconf/fconf_dyn_cfg_getter.h>
17 #include <lib/xlat_mpu/xlat_mpu.h>
18
19 #include "fvp_r_private.h"
20 #include <plat/arm/common/arm_config.h>
21 #include <plat/arm/common/arm_def.h>
22 #include <plat/arm/common/plat_arm.h>
23 #include <plat/common/platform.h>
24 #include <platform_def.h>
25
26 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \
27 bl1_tzram_layout.total_base, \
28 bl1_tzram_layout.total_size, \
29 MT_MEMORY | MT_RW | MT_SECURE)
30 /*
31 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
32 * otherwise one region is defined containing both
33 */
34 #if SEPARATE_CODE_AND_RODATA
35 #define MAP_BL1_RO MAP_REGION_FLAT( \
36 BL_CODE_BASE, \
37 BL1_CODE_END - BL_CODE_BASE, \
38 MT_CODE | MT_SECURE), \
39 MAP_REGION_FLAT( \
40 BL1_RO_DATA_BASE, \
41 BL1_RO_DATA_END \
42 - BL_RO_DATA_BASE, \
43 MT_RO_DATA | MT_SECURE)
44 #else
45 #define MAP_BL1_RO MAP_REGION_FLAT( \
46 BL_CODE_BASE, \
47 BL1_CODE_END - BL_CODE_BASE, \
48 MT_CODE | MT_SECURE)
49 #endif
50
51 /* Data structure which holds the extents of the trusted SRAM for BL1*/
52 static meminfo_t bl1_tzram_layout;
53
bl1_plat_sec_mem_layout(void)54 struct meminfo *bl1_plat_sec_mem_layout(void)
55 {
56 return &bl1_tzram_layout;
57 }
58
arm_bl1_early_platform_setup(void)59 void arm_bl1_early_platform_setup(void)
60 {
61
62 #if !ARM_DISABLE_TRUSTED_WDOG
63 /* Enable watchdog */
64 plat_arm_secure_wdt_start();
65 #endif
66
67 /* Initialize the console to provide early debug support */
68 arm_console_boot_init();
69
70 /* Allow BL1 to see the whole Trusted RAM */
71 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
72 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
73 }
74
75 /* Boolean variable to hold condition whether firmware update needed or not */
76 static bool is_fwu_needed;
77
78 /*******************************************************************************
79 * Perform any BL1 specific platform actions.
80 ******************************************************************************/
bl1_early_platform_setup(void)81 void bl1_early_platform_setup(void)
82 {
83 arm_bl1_early_platform_setup();
84
85 /* Initialize the platform config for future decision making */
86 fvp_config_setup();
87
88 /*
89 * Initialize Interconnect for this cluster during cold boot.
90 * No need for locks as no other CPU is active.
91 */
92 fvp_interconnect_init();
93 /*
94 * Enable coherency in Interconnect for the primary CPU's cluster.
95 */
96 fvp_interconnect_enable();
97 }
98
arm_bl1_plat_arch_setup(void)99 void arm_bl1_plat_arch_setup(void)
100 {
101 const mmap_region_t bl_regions[] = {
102 MAP_BL1_TOTAL,
103 MAP_BL1_RO,
104 #if USE_ROMLIB
105 ARM_MAP_ROMLIB_CODE,
106 ARM_MAP_ROMLIB_DATA,
107 #endif
108 #if ARM_CRYPTOCELL_INTEG
109 ARM_MAP_BL_COHERENT_RAM,
110 #endif
111 /* DRAM1_region: */
112 MAP_REGION_FLAT( \
113 PLAT_ARM_DRAM1_BASE, \
114 PLAT_ARM_DRAM1_SIZE, \
115 MT_MEMORY | MT_SECURE | MT_EXECUTE \
116 | MT_RW | MT_NON_CACHEABLE),
117 /* NULL terminator: */
118 {0}
119 };
120
121 setup_page_tables(bl_regions, plat_arm_get_mmap());
122 enable_mpu_el2(0);
123
124 arm_setup_romlib();
125 }
126
plat_arm_secure_wdt_start(void)127 void plat_arm_secure_wdt_start(void)
128 {
129 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
130 }
131
plat_arm_secure_wdt_stop(void)132 void plat_arm_secure_wdt_stop(void)
133 {
134 sp805_stop(ARM_SP805_TWDG_BASE);
135 }
136
137 /*
138 * Perform the platform specific architecture setup shared between
139 * ARM standard platforms.
140 */
arm_bl1_platform_setup(void)141 void arm_bl1_platform_setup(void)
142 {
143 uint32_t fw_config_max_size;
144
145 /* Initialise the IO layer and register platform IO devices */
146 plat_arm_io_setup();
147
148 /* Check if we need FWU before further processing */
149 is_fwu_needed = plat_arm_bl1_fwu_needed();
150 if (is_fwu_needed) {
151 ERROR("Skip platform setup as FWU detected\n");
152 return;
153 }
154
155 /* Set global DTB info for fixed fw_config information */
156 fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
157 set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size,
158 FW_CONFIG_ID);
159
160 assert(bl1_plat_get_image_desc(BL33_IMAGE_ID) != NULL);
161
162 /*
163 * Allow access to the System counter timer module and program
164 * counter frequency for non secure images during FWU
165 */
166 #ifdef ARM_SYS_TIMCTL_BASE
167 arm_configure_sys_timer();
168 #endif
169 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
170 write_cntfrq_el0(plat_get_syscnt_freq2());
171 #endif
172 }
173
bl1_platform_setup(void)174 void bl1_platform_setup(void)
175 {
176 arm_bl1_platform_setup();
177
178 /* Initialize System level generic or SP804 timer */
179 fvp_timer_init();
180 }
181
bl1_plat_fwu_done(void * client_cookie,void * reserved)182 __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
183 {
184 /* Setup the watchdog to reset the system as soon as possible */
185 sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
186
187 while (true) {
188 wfi();
189 }
190 }
191
bl1_plat_get_next_image_id(void)192 unsigned int bl1_plat_get_next_image_id(void)
193 {
194 return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL33_IMAGE_ID;
195 }
196
197 /*
198 * Returns BL33 image details.
199 */
bl1_plat_get_image_desc(unsigned int image_id)200 struct image_desc *bl1_plat_get_image_desc(unsigned int image_id)
201 {
202 static image_desc_t bl33_img_desc = BL33_IMAGE_DESC;
203
204 return &bl33_img_desc;
205 }
206
207 /*
208 * This function populates the default arguments to BL33.
209 * The BL33 memory layout structure is allocated and the
210 * calculated layout is populated in arg1 to BL33.
211 */
bl1_plat_handle_post_image_load(unsigned int image_id)212 int bl1_plat_handle_post_image_load(unsigned int image_id)
213 {
214 meminfo_t *bl33_secram_layout;
215 meminfo_t *bl1_secram_layout;
216 image_desc_t *image_desc;
217 entry_point_info_t *ep_info;
218
219 if (image_id != BL33_IMAGE_ID) {
220 return 0;
221 }
222 /* Get the image descriptor */
223 image_desc = bl1_plat_get_image_desc(BL33_IMAGE_ID);
224 assert(image_desc != NULL);
225
226 /* Get the entry point info */
227 ep_info = &image_desc->ep_info;
228
229 /* Find out how much free trusted ram remains after BL1 load */
230 bl1_secram_layout = bl1_plat_sec_mem_layout();
231
232 /*
233 * Create a new layout of memory for BL33 as seen by BL1 i.e.
234 * tell it the amount of total and free memory available.
235 * This layout is created at the first free address visible
236 * to BL33. BL33 will read the memory layout before using its
237 * memory for other purposes.
238 */
239 bl33_secram_layout = (meminfo_t *) bl1_secram_layout->total_base;
240
241 bl1_calc_bl2_mem_layout(bl1_secram_layout, bl33_secram_layout);
242
243 ep_info->args.arg1 = (uintptr_t)bl33_secram_layout;
244
245 VERBOSE("BL1: BL3 memory layout address = %p\n",
246 (void *) bl33_secram_layout);
247 return 0;
248 }
249
