1 /* 2 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DDR_H 8 #define STM32MP1_DDR_H 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 13 #include <drivers/st/stm32mp_ddr.h> 14 15 struct stm32mp1_ddrctrl_reg { 16 uint32_t mstr; 17 uint32_t mrctrl0; 18 uint32_t mrctrl1; 19 uint32_t derateen; 20 uint32_t derateint; 21 uint32_t pwrctl; 22 uint32_t pwrtmg; 23 uint32_t hwlpctl; 24 uint32_t rfshctl0; 25 uint32_t rfshctl3; 26 uint32_t crcparctl0; 27 uint32_t zqctl0; 28 uint32_t dfitmg0; 29 uint32_t dfitmg1; 30 uint32_t dfilpcfg0; 31 uint32_t dfiupd0; 32 uint32_t dfiupd1; 33 uint32_t dfiupd2; 34 uint32_t dfiphymstr; 35 uint32_t odtmap; 36 uint32_t dbg0; 37 uint32_t dbg1; 38 uint32_t dbgcmd; 39 uint32_t poisoncfg; 40 uint32_t pccfg; 41 }; 42 43 struct stm32mp1_ddrctrl_timing { 44 uint32_t rfshtmg; 45 uint32_t dramtmg0; 46 uint32_t dramtmg1; 47 uint32_t dramtmg2; 48 uint32_t dramtmg3; 49 uint32_t dramtmg4; 50 uint32_t dramtmg5; 51 uint32_t dramtmg6; 52 uint32_t dramtmg7; 53 uint32_t dramtmg8; 54 uint32_t dramtmg14; 55 uint32_t odtcfg; 56 }; 57 58 struct stm32mp1_ddrctrl_map { 59 uint32_t addrmap1; 60 uint32_t addrmap2; 61 uint32_t addrmap3; 62 uint32_t addrmap4; 63 uint32_t addrmap5; 64 uint32_t addrmap6; 65 uint32_t addrmap9; 66 uint32_t addrmap10; 67 uint32_t addrmap11; 68 }; 69 70 struct stm32mp1_ddrctrl_perf { 71 uint32_t sched; 72 uint32_t sched1; 73 uint32_t perfhpr1; 74 uint32_t perflpr1; 75 uint32_t perfwr1; 76 uint32_t pcfgr_0; 77 uint32_t pcfgw_0; 78 uint32_t pcfgqos0_0; 79 uint32_t pcfgqos1_0; 80 uint32_t pcfgwqos0_0; 81 uint32_t pcfgwqos1_0; 82 #if STM32MP_DDR_DUAL_AXI_PORT 83 uint32_t pcfgr_1; 84 uint32_t pcfgw_1; 85 uint32_t pcfgqos0_1; 86 uint32_t pcfgqos1_1; 87 uint32_t pcfgwqos0_1; 88 uint32_t pcfgwqos1_1; 89 #endif 90 }; 91 92 struct stm32mp1_ddrphy_reg { 93 uint32_t pgcr; 94 uint32_t aciocr; 95 uint32_t dxccr; 96 uint32_t dsgcr; 97 uint32_t dcr; 98 uint32_t odtcr; 99 uint32_t zq0cr1; 100 uint32_t dx0gcr; 101 uint32_t dx1gcr; 102 #if STM32MP_DDR_32BIT_INTERFACE 103 uint32_t dx2gcr; 104 uint32_t dx3gcr; 105 #endif 106 }; 107 108 struct stm32mp1_ddrphy_timing { 109 uint32_t ptr0; 110 uint32_t ptr1; 111 uint32_t ptr2; 112 uint32_t dtpr0; 113 uint32_t dtpr1; 114 uint32_t dtpr2; 115 uint32_t mr0; 116 uint32_t mr1; 117 uint32_t mr2; 118 uint32_t mr3; 119 }; 120 121 struct stm32mp_ddr_config { 122 struct stm32mp_ddr_info info; 123 struct stm32mp1_ddrctrl_reg c_reg; 124 struct stm32mp1_ddrctrl_timing c_timing; 125 struct stm32mp1_ddrctrl_map c_map; 126 struct stm32mp1_ddrctrl_perf c_perf; 127 struct stm32mp1_ddrphy_reg p_reg; 128 struct stm32mp1_ddrphy_timing p_timing; 129 }; 130 131 int stm32mp1_ddr_clk_enable(struct stm32mp_ddr_priv *priv, uint32_t mem_speed); 132 void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config); 133 134 #endif /* STM32MP1_DDR_H */ 135
