1 /*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <endian.h>
9 #include <errno.h>
10 #include <stdint.h>
11 #include <string.h>
12
13 #include <platform_def.h>
14
15 #include <arch_helpers.h>
16 #include <common/debug.h>
17 #include <drivers/delay_timer.h>
18 #include <drivers/ufs.h>
19 #include <lib/mmio.h>
20
21 #define CDB_ADDR_MASK 127
22 #define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK)
23 #define ALIGN_8(x) (((x) + 7) & ~7)
24
25 #define UFS_DESC_SIZE 0x400
26 #define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */
27
28 #define MAX_PRDT_SIZE 0x40000 /* 256KB */
29
30 static ufs_params_t ufs_params;
31 static int nutrs; /* Number of UTP Transfer Request Slots */
32
ufshc_send_uic_cmd(uintptr_t base,uic_cmd_t * cmd)33 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd)
34 {
35 unsigned int data;
36
37 if (base == 0 || cmd == NULL)
38 return -EINVAL;
39
40 data = mmio_read_32(base + HCS);
41 if ((data & HCS_UCRDY) == 0)
42 return -EBUSY;
43 mmio_write_32(base + IS, ~0);
44 mmio_write_32(base + UCMDARG1, cmd->arg1);
45 mmio_write_32(base + UCMDARG2, cmd->arg2);
46 mmio_write_32(base + UCMDARG3, cmd->arg3);
47 mmio_write_32(base + UICCMD, cmd->op);
48
49 do {
50 data = mmio_read_32(base + IS);
51 } while ((data & UFS_INT_UCCS) == 0);
52 mmio_write_32(base + IS, UFS_INT_UCCS);
53 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK;
54 }
55
ufshc_dme_get(unsigned int attr,unsigned int idx,unsigned int * val)56 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val)
57 {
58 uintptr_t base;
59 unsigned int data;
60 int result, retries;
61 uic_cmd_t cmd;
62
63 assert(ufs_params.reg_base != 0);
64
65 if (val == NULL)
66 return -EINVAL;
67
68 base = ufs_params.reg_base;
69 for (retries = 0; retries < 100; retries++) {
70 data = mmio_read_32(base + HCS);
71 if ((data & HCS_UCRDY) != 0)
72 break;
73 mdelay(1);
74 }
75 if (retries >= 100)
76 return -EBUSY;
77
78 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
79 cmd.arg2 = 0;
80 cmd.arg3 = 0;
81 cmd.op = DME_GET;
82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
83 result = ufshc_send_uic_cmd(base, &cmd);
84 if (result == 0)
85 break;
86 data = mmio_read_32(base + IS);
87 if (data & UFS_INT_UE)
88 return -EINVAL;
89 }
90 if (retries >= UFS_UIC_COMMAND_RETRIES)
91 return -EIO;
92
93 *val = mmio_read_32(base + UCMDARG3);
94 return 0;
95 }
96
ufshc_dme_set(unsigned int attr,unsigned int idx,unsigned int val)97 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val)
98 {
99 uintptr_t base;
100 unsigned int data;
101 int result, retries;
102 uic_cmd_t cmd;
103
104 assert((ufs_params.reg_base != 0));
105
106 base = ufs_params.reg_base;
107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
108 cmd.arg2 = 0;
109 cmd.arg3 = val;
110 cmd.op = DME_SET;
111
112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
113 result = ufshc_send_uic_cmd(base, &cmd);
114 if (result == 0)
115 break;
116 data = mmio_read_32(base + IS);
117 if (data & UFS_INT_UE)
118 return -EINVAL;
119 }
120 if (retries >= UFS_UIC_COMMAND_RETRIES)
121 return -EIO;
122
123 return 0;
124 }
125
ufshc_hce_enable(uintptr_t base)126 static int ufshc_hce_enable(uintptr_t base)
127 {
128 unsigned int data;
129 int retries;
130
131 /* Enable Host Controller */
132 mmio_write_32(base + HCE, HCE_ENABLE);
133
134 /* Wait until basic initialization sequence completed */
135 for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) {
136 data = mmio_read_32(base + HCE);
137 if (data & HCE_ENABLE) {
138 break;
139 }
140 udelay(HCE_ENABLE_TIMEOUT_US);
141 }
142 if (retries >= HCE_ENABLE_INNER_RETRIES) {
143 return -ETIMEDOUT;
144 }
145
146 return 0;
147 }
148
ufshc_hce_disable(uintptr_t base)149 static int ufshc_hce_disable(uintptr_t base)
150 {
151 unsigned int data;
152 int timeout;
153
154 /* Disable Host Controller */
155 mmio_write_32(base + HCE, HCE_DISABLE);
156 timeout = HCE_DISABLE_TIMEOUT_US;
157 do {
158 data = mmio_read_32(base + HCE);
159 if ((data & HCE_ENABLE) == HCE_DISABLE) {
160 break;
161 }
162 udelay(1);
163 } while (--timeout > 0);
164
165 if (timeout <= 0) {
166 return -ETIMEDOUT;
167 }
168
169 return 0;
170 }
171
172
ufshc_reset(uintptr_t base)173 static int ufshc_reset(uintptr_t base)
174 {
175 unsigned int data;
176 int retries, result;
177
178 /* disable controller if enabled */
179 if (mmio_read_32(base + HCE) & HCE_ENABLE) {
180 result = ufshc_hce_disable(base);
181 if (result != 0) {
182 return -EIO;
183 }
184 }
185
186 for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) {
187 result = ufshc_hce_enable(base);
188 if (result == 0) {
189 break;
190 }
191 }
192 if (retries >= HCE_ENABLE_OUTER_RETRIES) {
193 return -EIO;
194 }
195
196 /* Enable Interrupts */
197 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES |
198 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES;
199 mmio_write_32(base + IE, data);
200
201 return 0;
202 }
203
ufshc_dme_link_startup(uintptr_t base)204 static int ufshc_dme_link_startup(uintptr_t base)
205 {
206 uic_cmd_t cmd;
207
208 memset(&cmd, 0, sizeof(cmd));
209 cmd.op = DME_LINKSTARTUP;
210 return ufshc_send_uic_cmd(base, &cmd);
211 }
212
ufshc_link_startup(uintptr_t base)213 static int ufshc_link_startup(uintptr_t base)
214 {
215 int data, result;
216 int retries;
217
218 for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) {
219 result = ufshc_dme_link_startup(base);
220 if (result != 0) {
221 /* Reset controller before trying again */
222 result = ufshc_reset(base);
223 if (result != 0) {
224 return result;
225 }
226 continue;
227 }
228 assert((mmio_read_32(base + HCS) & HCS_DP) == 0);
229 data = mmio_read_32(base + IS);
230 if (data & UFS_INT_ULSS)
231 mmio_write_32(base + IS, UFS_INT_ULSS);
232 return 0;
233 }
234 return -EIO;
235 }
236
237 /* Check Door Bell register to get an empty slot */
get_empty_slot(int * slot)238 static int get_empty_slot(int *slot)
239 {
240 unsigned int data;
241 int i;
242
243 data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
244 for (i = 0; i < nutrs; i++) {
245 if ((data & 1) == 0)
246 break;
247 data = data >> 1;
248 }
249 if (i >= nutrs)
250 return -EBUSY;
251 *slot = i;
252 return 0;
253 }
254
get_utrd(utp_utrd_t * utrd)255 static void get_utrd(utp_utrd_t *utrd)
256 {
257 uintptr_t base;
258 int slot = 0, result;
259 utrd_header_t *hd;
260
261 assert(utrd != NULL);
262 result = get_empty_slot(&slot);
263 assert(result == 0);
264
265 /* clear utrd */
266 memset((void *)utrd, 0, sizeof(utp_utrd_t));
267 base = ufs_params.desc_base + (slot * UFS_DESC_SIZE);
268 /* clear the descriptor */
269 memset((void *)base, 0, UFS_DESC_SIZE);
270
271 utrd->header = base;
272 utrd->task_tag = slot + 1;
273 /* CDB address should be aligned with 128 bytes */
274 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t));
275 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t));
276 utrd->size_upiu = utrd->resp_upiu - utrd->upiu;
277 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t));
278 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu;
279
280 hd = (utrd_header_t *)utrd->header;
281 hd->ucdba = utrd->upiu & UINT32_MAX;
282 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX;
283 /* Both RUL and RUO is based on DWORD */
284 hd->rul = utrd->size_resp_upiu >> 2;
285 hd->ruo = utrd->size_upiu >> 2;
286 (void)result;
287 }
288
289 /*
290 * Prepare UTRD, Command UPIU, Response UPIU.
291 */
ufs_prepare_cmd(utp_utrd_t * utrd,uint8_t op,uint8_t lun,int lba,uintptr_t buf,size_t length)292 static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun,
293 int lba, uintptr_t buf, size_t length)
294 {
295 utrd_header_t *hd;
296 cmd_upiu_t *upiu;
297 prdt_t *prdt;
298 unsigned int ulba;
299 unsigned int lba_cnt;
300 int prdt_size;
301
302
303 mmio_write_32(ufs_params.reg_base + UTRLBA,
304 utrd->header & UINT32_MAX);
305 mmio_write_32(ufs_params.reg_base + UTRLBAU,
306 (utrd->upiu >> 32) & UINT32_MAX);
307
308 hd = (utrd_header_t *)utrd->header;
309 upiu = (cmd_upiu_t *)utrd->upiu;
310
311 hd->i = 1;
312 hd->ct = CT_UFS_STORAGE;
313 hd->ocs = OCS_MASK;
314
315 upiu->trans_type = CMD_UPIU;
316 upiu->task_tag = utrd->task_tag;
317 upiu->cdb[0] = op;
318 ulba = (unsigned int)lba;
319 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT);
320 switch (op) {
321 case CDBCMD_TEST_UNIT_READY:
322 break;
323 case CDBCMD_READ_CAPACITY_10:
324 hd->dd = DD_OUT;
325 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
326 upiu->lun = lun;
327 break;
328 case CDBCMD_READ_10:
329 hd->dd = DD_OUT;
330 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
331 upiu->lun = lun;
332 upiu->cdb[1] = RW_WITHOUT_CACHE;
333 /* set logical block address */
334 upiu->cdb[2] = (ulba >> 24) & 0xff;
335 upiu->cdb[3] = (ulba >> 16) & 0xff;
336 upiu->cdb[4] = (ulba >> 8) & 0xff;
337 upiu->cdb[5] = ulba & 0xff;
338 /* set transfer length */
339 upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
340 upiu->cdb[8] = lba_cnt & 0xff;
341 break;
342 case CDBCMD_WRITE_10:
343 hd->dd = DD_IN;
344 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S;
345 upiu->lun = lun;
346 upiu->cdb[1] = RW_WITHOUT_CACHE;
347 /* set logical block address */
348 upiu->cdb[2] = (ulba >> 24) & 0xff;
349 upiu->cdb[3] = (ulba >> 16) & 0xff;
350 upiu->cdb[4] = (ulba >> 8) & 0xff;
351 upiu->cdb[5] = ulba & 0xff;
352 /* set transfer length */
353 upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
354 upiu->cdb[8] = lba_cnt & 0xff;
355 break;
356 default:
357 assert(0);
358 break;
359 }
360 if (hd->dd == DD_IN)
361 flush_dcache_range(buf, length);
362 else if (hd->dd == DD_OUT)
363 inv_dcache_range(buf, length);
364 if (length) {
365 upiu->exp_data_trans_len = htobe32(length);
366 assert(lba_cnt <= UINT16_MAX);
367 prdt = (prdt_t *)utrd->prdt;
368
369 prdt_size = 0;
370 while (length > 0) {
371 prdt->dba = (unsigned int)(buf & UINT32_MAX);
372 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX);
373 /* prdt->dbc counts from 0 */
374 if (length > MAX_PRDT_SIZE) {
375 prdt->dbc = MAX_PRDT_SIZE - 1;
376 length = length - MAX_PRDT_SIZE;
377 } else {
378 prdt->dbc = length - 1;
379 length = 0;
380 }
381 buf += MAX_PRDT_SIZE;
382 prdt++;
383 prdt_size += sizeof(prdt_t);
384 }
385 utrd->size_prdt = ALIGN_8(prdt_size);
386 hd->prdtl = utrd->size_prdt >> 2;
387 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2;
388 }
389
390 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
391 return 0;
392 }
393
ufs_prepare_query(utp_utrd_t * utrd,uint8_t op,uint8_t idn,uint8_t index,uint8_t sel,uintptr_t buf,size_t length)394 static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn,
395 uint8_t index, uint8_t sel,
396 uintptr_t buf, size_t length)
397 {
398 utrd_header_t *hd;
399 query_upiu_t *query_upiu;
400
401
402 hd = (utrd_header_t *)utrd->header;
403 query_upiu = (query_upiu_t *)utrd->upiu;
404
405 mmio_write_32(ufs_params.reg_base + UTRLBA,
406 utrd->header & UINT32_MAX);
407 mmio_write_32(ufs_params.reg_base + UTRLBAU,
408 (utrd->header >> 32) & UINT32_MAX);
409
410
411 hd->i = 1;
412 hd->ct = CT_UFS_STORAGE;
413 hd->ocs = OCS_MASK;
414
415 query_upiu->trans_type = QUERY_REQUEST_UPIU;
416 query_upiu->task_tag = utrd->task_tag;
417 query_upiu->ts.desc.opcode = op;
418 query_upiu->ts.desc.idn = idn;
419 query_upiu->ts.desc.index = index;
420 query_upiu->ts.desc.selector = sel;
421 switch (op) {
422 case QUERY_READ_DESC:
423 query_upiu->query_func = QUERY_FUNC_STD_READ;
424 query_upiu->ts.desc.length = htobe16(length);
425 break;
426 case QUERY_WRITE_DESC:
427 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
428 query_upiu->ts.desc.length = htobe16(length);
429 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)),
430 (void *)buf, length);
431 break;
432 case QUERY_READ_ATTR:
433 case QUERY_READ_FLAG:
434 query_upiu->query_func = QUERY_FUNC_STD_READ;
435 break;
436 case QUERY_CLEAR_FLAG:
437 case QUERY_SET_FLAG:
438 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
439 break;
440 case QUERY_WRITE_ATTR:
441 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
442 query_upiu->ts.attr.value = htobe32(*((uint32_t *)buf));
443 break;
444 default:
445 assert(0);
446 break;
447 }
448 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
449 return 0;
450 }
451
ufs_prepare_nop_out(utp_utrd_t * utrd)452 static void ufs_prepare_nop_out(utp_utrd_t *utrd)
453 {
454 utrd_header_t *hd;
455 nop_out_upiu_t *nop_out;
456
457 mmio_write_32(ufs_params.reg_base + UTRLBA,
458 utrd->header & UINT32_MAX);
459 mmio_write_32(ufs_params.reg_base + UTRLBAU,
460 (utrd->header >> 32) & UINT32_MAX);
461
462 hd = (utrd_header_t *)utrd->header;
463 nop_out = (nop_out_upiu_t *)utrd->upiu;
464
465 hd->i = 1;
466 hd->ct = CT_UFS_STORAGE;
467 hd->ocs = OCS_MASK;
468
469 nop_out->trans_type = 0;
470 nop_out->task_tag = utrd->task_tag;
471 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
472 }
473
ufs_send_request(int task_tag)474 static void ufs_send_request(int task_tag)
475 {
476 unsigned int data;
477 int slot;
478
479 slot = task_tag - 1;
480 /* clear all interrupts */
481 mmio_write_32(ufs_params.reg_base + IS, ~0);
482
483 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1);
484 assert(mmio_read_32(ufs_params.reg_base + UTRLRSR) == 1);
485
486 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) |
487 UTRIACR_IATOVAL(0xFF);
488 mmio_write_32(ufs_params.reg_base + UTRIACR, data);
489 /* send request */
490 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot);
491 }
492
ufs_check_resp(utp_utrd_t * utrd,int trans_type)493 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type)
494 {
495 utrd_header_t *hd;
496 resp_upiu_t *resp;
497 unsigned int data;
498 int slot;
499
500 hd = (utrd_header_t *)utrd->header;
501 resp = (resp_upiu_t *)utrd->resp_upiu;
502 do {
503 data = mmio_read_32(ufs_params.reg_base + IS);
504 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0)
505 return -EIO;
506 } while ((data & UFS_INT_UTRCS) == 0);
507 slot = utrd->task_tag - 1;
508
509 data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
510 assert((data & (1 << slot)) == 0);
511 /*
512 * Invalidate the header after DMA read operation has
513 * completed to avoid cpu referring to the prefetched
514 * data brought in before DMA completion.
515 */
516 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE);
517 assert(hd->ocs == OCS_SUCCESS);
518 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type);
519 (void)resp;
520 (void)slot;
521 return 0;
522 }
523
ufs_send_cmd(utp_utrd_t * utrd,uint8_t cmd_op,uint8_t lun,int lba,uintptr_t buf,size_t length)524 static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf,
525 size_t length)
526 {
527 int result;
528
529 get_utrd(utrd);
530
531 result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length);
532 assert(result == 0);
533 ufs_send_request(utrd->task_tag);
534 result = ufs_check_resp(utrd, RESPONSE_UPIU);
535 assert(result == 0);
536 (void)result;
537 }
538
539 #ifdef UFS_RESP_DEBUG
dump_upiu(utp_utrd_t * utrd)540 static void dump_upiu(utp_utrd_t *utrd)
541 {
542 utrd_header_t *hd;
543 int i;
544
545 hd = (utrd_header_t *)utrd->header;
546 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n",
547 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs,
548 mmio_read_32(ufs_params.reg_base + UTRLDBR));
549 for (i = 0; i < sizeof(utrd_header_t); i += 4) {
550 INFO("[%lx]:0x%x\n",
551 (uintptr_t)utrd->header + i,
552 *(unsigned int *)((uintptr_t)utrd->header + i));
553 }
554
555 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) {
556 INFO("cmd[%lx]:0x%x\n",
557 utrd->upiu + i,
558 *(unsigned int *)(utrd->upiu + i));
559 }
560 for (i = 0; i < sizeof(resp_upiu_t); i += 4) {
561 INFO("resp[%lx]:0x%x\n",
562 utrd->resp_upiu + i,
563 *(unsigned int *)(utrd->resp_upiu + i));
564 }
565 for (i = 0; i < sizeof(prdt_t); i += 4) {
566 INFO("prdt[%lx]:0x%x\n",
567 utrd->prdt + i,
568 *(unsigned int *)(utrd->prdt + i));
569 }
570 }
571 #endif
572
ufs_verify_init(void)573 static void ufs_verify_init(void)
574 {
575 utp_utrd_t utrd;
576 int result;
577
578 get_utrd(&utrd);
579 ufs_prepare_nop_out(&utrd);
580 ufs_send_request(utrd.task_tag);
581 result = ufs_check_resp(&utrd, NOP_IN_UPIU);
582 assert(result == 0);
583 (void)result;
584 }
585
ufs_verify_ready(void)586 static void ufs_verify_ready(void)
587 {
588 utp_utrd_t utrd;
589 ufs_send_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0);
590 }
591
ufs_query(uint8_t op,uint8_t idn,uint8_t index,uint8_t sel,uintptr_t buf,size_t size)592 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
593 uintptr_t buf, size_t size)
594 {
595 utp_utrd_t utrd;
596 query_resp_upiu_t *resp;
597 int result;
598
599 switch (op) {
600 case QUERY_READ_FLAG:
601 case QUERY_READ_ATTR:
602 case QUERY_READ_DESC:
603 case QUERY_WRITE_DESC:
604 case QUERY_WRITE_ATTR:
605 assert(((buf & 3) == 0) && (size != 0));
606 break;
607 default:
608 /* Do nothing in default case */
609 break;
610 }
611 get_utrd(&utrd);
612 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size);
613 ufs_send_request(utrd.task_tag);
614 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU);
615 assert(result == 0);
616 resp = (query_resp_upiu_t *)utrd.resp_upiu;
617 #ifdef UFS_RESP_DEBUG
618 dump_upiu(&utrd);
619 #endif
620 assert(resp->query_resp == QUERY_RESP_SUCCESS);
621
622 switch (op) {
623 case QUERY_READ_FLAG:
624 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value;
625 break;
626 case QUERY_READ_DESC:
627 memcpy((void *)buf,
628 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)),
629 size);
630 break;
631 case QUERY_READ_ATTR:
632 *(uint32_t *)buf = htobe32(resp->ts.attr.value);
633 break;
634 default:
635 /* Do nothing in default case */
636 break;
637 }
638 (void)result;
639 }
640
ufs_read_attr(int idn)641 unsigned int ufs_read_attr(int idn)
642 {
643 unsigned int value;
644
645 ufs_query(QUERY_READ_ATTR, idn, 0, 0,
646 (uintptr_t)&value, sizeof(value));
647 return value;
648 }
649
ufs_write_attr(int idn,unsigned int value)650 void ufs_write_attr(int idn, unsigned int value)
651 {
652 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0,
653 (uintptr_t)&value, sizeof(value));
654 }
655
ufs_read_flag(int idn)656 unsigned int ufs_read_flag(int idn)
657 {
658 unsigned int value;
659
660 ufs_query(QUERY_READ_FLAG, idn, 0, 0,
661 (uintptr_t)&value, sizeof(value));
662 return value;
663 }
664
ufs_set_flag(int idn)665 void ufs_set_flag(int idn)
666 {
667 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0);
668 }
669
ufs_clear_flag(int idn)670 void ufs_clear_flag(int idn)
671 {
672 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0);
673 }
674
ufs_read_desc(int idn,int index,uintptr_t buf,size_t size)675 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size)
676 {
677 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size);
678 }
679
ufs_write_desc(int idn,int index,uintptr_t buf,size_t size)680 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size)
681 {
682 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size);
683 }
684
ufs_read_capacity(int lun,unsigned int * num,unsigned int * size)685 static void ufs_read_capacity(int lun, unsigned int *num, unsigned int *size)
686 {
687 utp_utrd_t utrd;
688 resp_upiu_t *resp;
689 sense_data_t *sense;
690 unsigned char data[CACHE_WRITEBACK_GRANULE << 1];
691 uintptr_t buf;
692 int retry;
693
694 assert((ufs_params.reg_base != 0) &&
695 (ufs_params.desc_base != 0) &&
696 (ufs_params.desc_size >= UFS_DESC_SIZE) &&
697 (num != NULL) && (size != NULL));
698
699 /* align buf address */
700 buf = (uintptr_t)data;
701 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) &
702 ~(CACHE_WRITEBACK_GRANULE - 1);
703 do {
704 ufs_send_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0,
705 buf, READ_CAPACITY_LENGTH);
706 #ifdef UFS_RESP_DEBUG
707 dump_upiu(&utrd);
708 #endif
709 resp = (resp_upiu_t *)utrd.resp_upiu;
710 retry = 0;
711 sense = &resp->sd.sense;
712 if (sense->resp_code == SENSE_DATA_VALID) {
713 if ((sense->sense_key == SENSE_KEY_UNIT_ATTENTION) &&
714 (sense->asc == 0x29) && (sense->ascq == 0)) {
715 retry = 1;
716 }
717 }
718 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE);
719 /* last logical block address */
720 *num = be32toh(*(unsigned int *)buf);
721 if (*num)
722 *num += 1;
723 /* logical block length in bytes */
724 *size = be32toh(*(unsigned int *)(buf + 4));
725 } while (retry);
726 }
727
ufs_read_blocks(int lun,int lba,uintptr_t buf,size_t size)728 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size)
729 {
730 utp_utrd_t utrd;
731 resp_upiu_t *resp;
732
733 assert((ufs_params.reg_base != 0) &&
734 (ufs_params.desc_base != 0) &&
735 (ufs_params.desc_size >= UFS_DESC_SIZE));
736
737 ufs_send_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size);
738 #ifdef UFS_RESP_DEBUG
739 dump_upiu(&utrd);
740 #endif
741 /*
742 * Invalidate prefetched cache contents before cpu
743 * accesses the buf.
744 */
745 inv_dcache_range(buf, size);
746 resp = (resp_upiu_t *)utrd.resp_upiu;
747 return size - resp->res_trans_cnt;
748 }
749
ufs_write_blocks(int lun,int lba,const uintptr_t buf,size_t size)750 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size)
751 {
752 utp_utrd_t utrd;
753 resp_upiu_t *resp;
754
755 assert((ufs_params.reg_base != 0) &&
756 (ufs_params.desc_base != 0) &&
757 (ufs_params.desc_size >= UFS_DESC_SIZE));
758
759 ufs_send_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size);
760 #ifdef UFS_RESP_DEBUG
761 dump_upiu(&utrd);
762 #endif
763 resp = (resp_upiu_t *)utrd.resp_upiu;
764 return size - resp->res_trans_cnt;
765 }
766
ufs_set_fdevice_init(void)767 static int ufs_set_fdevice_init(void)
768 {
769 unsigned int result;
770 int timeout;
771
772 ufs_set_flag(FLAG_DEVICE_INIT);
773
774 timeout = FDEVICEINIT_TIMEOUT_MS;
775 do {
776 result = ufs_read_flag(FLAG_DEVICE_INIT);
777 if (!result) {
778 break;
779 }
780 mdelay(5);
781 timeout -= 5;
782 } while (timeout > 0);
783
784 if (result != 0U) {
785 return -ETIMEDOUT;
786 }
787
788 return 0;
789 }
790
ufs_enum(void)791 static void ufs_enum(void)
792 {
793 unsigned int blk_num, blk_size;
794 int i, result;
795
796 ufs_verify_init();
797 ufs_verify_ready();
798
799 result = ufs_set_fdevice_init();
800 assert(result == 0);
801
802 /* dump available LUNs */
803 for (i = 0; i < UFS_MAX_LUNS; i++) {
804 ufs_read_capacity(i, &blk_num, &blk_size);
805 if (blk_num && blk_size) {
806 INFO("UFS LUN%d contains %d blocks with %d-byte size\n",
807 i, blk_num, blk_size);
808 }
809 }
810
811 (void)result;
812 }
813
ufs_get_device_info(struct ufs_dev_desc * card_data)814 static void ufs_get_device_info(struct ufs_dev_desc *card_data)
815 {
816 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE];
817
818 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0,
819 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE);
820
821 /*
822 * getting vendor (manufacturerID) and Bank Index in big endian
823 * format
824 */
825 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) |
826 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]));
827 }
828
ufs_init(const ufs_ops_t * ops,ufs_params_t * params)829 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params)
830 {
831 int result;
832 unsigned int data;
833 uic_cmd_t cmd;
834 struct ufs_dev_desc card = {0};
835
836 assert((params != NULL) &&
837 (params->reg_base != 0) &&
838 (params->desc_base != 0) &&
839 (params->desc_size >= UFS_DESC_SIZE));
840
841 memcpy(&ufs_params, params, sizeof(ufs_params_t));
842
843 /* 0 means 1 slot */
844 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1;
845 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) {
846 nutrs = ufs_params.desc_size / UFS_DESC_SIZE;
847 }
848
849
850 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) {
851 result = ufshc_dme_get(0x1571, 0, &data);
852 assert(result == 0);
853 result = ufshc_dme_get(0x41, 0, &data);
854 assert(result == 0);
855 if (data == 1) {
856 /* prepare to exit hibernate mode */
857 memset(&cmd, 0, sizeof(uic_cmd_t));
858 cmd.op = DME_HIBERNATE_EXIT;
859 result = ufshc_send_uic_cmd(ufs_params.reg_base,
860 &cmd);
861 assert(result == 0);
862 data = mmio_read_32(ufs_params.reg_base + UCMDARG2);
863 assert(data == 0);
864 do {
865 data = mmio_read_32(ufs_params.reg_base + IS);
866 } while ((data & UFS_INT_UHXS) == 0);
867 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS);
868 data = mmio_read_32(ufs_params.reg_base + HCS);
869 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL);
870 }
871 result = ufshc_dme_get(0x1568, 0, &data);
872 assert(result == 0);
873 assert((data > 0) && (data <= 3));
874 } else {
875 assert((ops != NULL) && (ops->phy_init != NULL) &&
876 (ops->phy_set_pwr_mode != NULL));
877
878 result = ufshc_reset(ufs_params.reg_base);
879 assert(result == 0);
880 ops->phy_init(&ufs_params);
881 result = ufshc_link_startup(ufs_params.reg_base);
882 assert(result == 0);
883
884 ufs_enum();
885
886 ufs_get_device_info(&card);
887 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) {
888 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX;
889 }
890
891 ops->phy_set_pwr_mode(&ufs_params);
892 }
893
894 (void)result;
895 return 0;
896 }
897
