1 /*
2 * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h> /* for uint32_t */
8
9 #include <lib/mmio.h>
10
11 #include "pfc_init_g2m.h"
12 #include "rcar_def.h"
13 #include "rcar_private.h"
14 #include "pfc_regs.h"
15
16 #define GPSR0_D15 BIT(15)
17 #define GPSR0_D14 BIT(14)
18 #define GPSR0_D13 BIT(13)
19 #define GPSR0_D12 BIT(12)
20 #define GPSR0_D11 BIT(11)
21 #define GPSR0_D10 BIT(10)
22 #define GPSR0_D9 BIT(9)
23 #define GPSR0_D8 BIT(8)
24 #define GPSR0_D7 BIT(7)
25 #define GPSR0_D6 BIT(6)
26 #define GPSR0_D5 BIT(5)
27 #define GPSR0_D4 BIT(4)
28 #define GPSR0_D3 BIT(3)
29 #define GPSR0_D2 BIT(2)
30 #define GPSR0_D1 BIT(1)
31 #define GPSR0_D0 BIT(0)
32 #define GPSR1_CLKOUT BIT(28)
33 #define GPSR1_EX_WAIT0_A BIT(27)
34 #define GPSR1_WE1 BIT(26)
35 #define GPSR1_WE0 BIT(25)
36 #define GPSR1_RD_WR BIT(24)
37 #define GPSR1_RD BIT(23)
38 #define GPSR1_BS BIT(22)
39 #define GPSR1_CS1_A26 BIT(21)
40 #define GPSR1_CS0 BIT(20)
41 #define GPSR1_A19 BIT(19)
42 #define GPSR1_A18 BIT(18)
43 #define GPSR1_A17 BIT(17)
44 #define GPSR1_A16 BIT(16)
45 #define GPSR1_A15 BIT(15)
46 #define GPSR1_A14 BIT(14)
47 #define GPSR1_A13 BIT(13)
48 #define GPSR1_A12 BIT(12)
49 #define GPSR1_A11 BIT(11)
50 #define GPSR1_A10 BIT(10)
51 #define GPSR1_A9 BIT(9)
52 #define GPSR1_A8 BIT(8)
53 #define GPSR1_A7 BIT(7)
54 #define GPSR1_A6 BIT(6)
55 #define GPSR1_A5 BIT(5)
56 #define GPSR1_A4 BIT(4)
57 #define GPSR1_A3 BIT(3)
58 #define GPSR1_A2 BIT(2)
59 #define GPSR1_A1 BIT(1)
60 #define GPSR1_A0 BIT(0)
61 #define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
62 #define GPSR2_AVB_AVTP_MATCH_A BIT(13)
63 #define GPSR2_AVB_LINK BIT(12)
64 #define GPSR2_AVB_PHY_INT BIT(11)
65 #define GPSR2_AVB_MAGIC BIT(10)
66 #define GPSR2_AVB_MDC BIT(9)
67 #define GPSR2_PWM2_A BIT(8)
68 #define GPSR2_PWM1_A BIT(7)
69 #define GPSR2_PWM0 BIT(6)
70 #define GPSR2_IRQ5 BIT(5)
71 #define GPSR2_IRQ4 BIT(4)
72 #define GPSR2_IRQ3 BIT(3)
73 #define GPSR2_IRQ2 BIT(2)
74 #define GPSR2_IRQ1 BIT(1)
75 #define GPSR2_IRQ0 BIT(0)
76 #define GPSR3_SD1_WP BIT(15)
77 #define GPSR3_SD1_CD BIT(14)
78 #define GPSR3_SD0_WP BIT(13)
79 #define GPSR3_SD0_CD BIT(12)
80 #define GPSR3_SD1_DAT3 BIT(11)
81 #define GPSR3_SD1_DAT2 BIT(10)
82 #define GPSR3_SD1_DAT1 BIT(9)
83 #define GPSR3_SD1_DAT0 BIT(8)
84 #define GPSR3_SD1_CMD BIT(7)
85 #define GPSR3_SD1_CLK BIT(6)
86 #define GPSR3_SD0_DAT3 BIT(5)
87 #define GPSR3_SD0_DAT2 BIT(4)
88 #define GPSR3_SD0_DAT1 BIT(3)
89 #define GPSR3_SD0_DAT0 BIT(2)
90 #define GPSR3_SD0_CMD BIT(1)
91 #define GPSR3_SD0_CLK BIT(0)
92 #define GPSR4_SD3_DS BIT(17)
93 #define GPSR4_SD3_DAT7 BIT(16)
94 #define GPSR4_SD3_DAT6 BIT(15)
95 #define GPSR4_SD3_DAT5 BIT(14)
96 #define GPSR4_SD3_DAT4 BIT(13)
97 #define GPSR4_SD3_DAT3 BIT(12)
98 #define GPSR4_SD3_DAT2 BIT(11)
99 #define GPSR4_SD3_DAT1 BIT(10)
100 #define GPSR4_SD3_DAT0 BIT(9)
101 #define GPSR4_SD3_CMD BIT(8)
102 #define GPSR4_SD3_CLK BIT(7)
103 #define GPSR4_SD2_DS BIT(6)
104 #define GPSR4_SD2_DAT3 BIT(5)
105 #define GPSR4_SD2_DAT2 BIT(4)
106 #define GPSR4_SD2_DAT1 BIT(3)
107 #define GPSR4_SD2_DAT0 BIT(2)
108 #define GPSR4_SD2_CMD BIT(1)
109 #define GPSR4_SD2_CLK BIT(0)
110 #define GPSR5_MLB_DAT BIT(25)
111 #define GPSR5_MLB_SIG BIT(24)
112 #define GPSR5_MLB_CLK BIT(23)
113 #define GPSR5_MSIOF0_RXD BIT(22)
114 #define GPSR5_MSIOF0_SS2 BIT(21)
115 #define GPSR5_MSIOF0_TXD BIT(20)
116 #define GPSR5_MSIOF0_SS1 BIT(19)
117 #define GPSR5_MSIOF0_SYNC BIT(18)
118 #define GPSR5_MSIOF0_SCK BIT(17)
119 #define GPSR5_HRTS0 BIT(16)
120 #define GPSR5_HCTS0 BIT(15)
121 #define GPSR5_HTX0 BIT(14)
122 #define GPSR5_HRX0 BIT(13)
123 #define GPSR5_HSCK0 BIT(12)
124 #define GPSR5_RX2_A BIT(11)
125 #define GPSR5_TX2_A BIT(10)
126 #define GPSR5_SCK2 BIT(9)
127 #define GPSR5_RTS1 BIT(8)
128 #define GPSR5_CTS1 BIT(7)
129 #define GPSR5_TX1_A BIT(6)
130 #define GPSR5_RX1_A BIT(5)
131 #define GPSR5_RTS0 BIT(4)
132 #define GPSR5_CTS0 BIT(3)
133 #define GPSR5_TX0 BIT(2)
134 #define GPSR5_RX0 BIT(1)
135 #define GPSR5_SCK0 BIT(0)
136 #define GPSR6_USB31_OVC BIT(31)
137 #define GPSR6_USB31_PWEN BIT(30)
138 #define GPSR6_USB30_OVC BIT(29)
139 #define GPSR6_USB30_PWEN BIT(28)
140 #define GPSR6_USB1_OVC BIT(27)
141 #define GPSR6_USB1_PWEN BIT(26)
142 #define GPSR6_USB0_OVC BIT(25)
143 #define GPSR6_USB0_PWEN BIT(24)
144 #define GPSR6_AUDIO_CLKB_B BIT(23)
145 #define GPSR6_AUDIO_CLKA_A BIT(22)
146 #define GPSR6_SSI_SDATA9_A BIT(21)
147 #define GPSR6_SSI_SDATA8 BIT(20)
148 #define GPSR6_SSI_SDATA7 BIT(19)
149 #define GPSR6_SSI_WS78 BIT(18)
150 #define GPSR6_SSI_SCK78 BIT(17)
151 #define GPSR6_SSI_SDATA6 BIT(16)
152 #define GPSR6_SSI_WS6 BIT(15)
153 #define GPSR6_SSI_SCK6 BIT(14)
154 #define GPSR6_SSI_SDATA5 BIT(13)
155 #define GPSR6_SSI_WS5 BIT(12)
156 #define GPSR6_SSI_SCK5 BIT(11)
157 #define GPSR6_SSI_SDATA4 BIT(10)
158 #define GPSR6_SSI_WS4 BIT(9)
159 #define GPSR6_SSI_SCK4 BIT(8)
160 #define GPSR6_SSI_SDATA3 BIT(7)
161 #define GPSR6_SSI_WS34 BIT(6)
162 #define GPSR6_SSI_SCK34 BIT(5)
163 #define GPSR6_SSI_SDATA2_A BIT(4)
164 #define GPSR6_SSI_SDATA1_A BIT(3)
165 #define GPSR6_SSI_SDATA0 BIT(2)
166 #define GPSR6_SSI_WS0129 BIT(1)
167 #define GPSR6_SSI_SCK0129 BIT(0)
168 #define GPSR7_AVS2 BIT(1)
169 #define GPSR7_AVS1 BIT(0)
170
171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
179
180 #define POC_SD3_DS_33V BIT(29)
181 #define POC_SD3_DAT7_33V BIT(28)
182 #define POC_SD3_DAT6_33V BIT(27)
183 #define POC_SD3_DAT5_33V BIT(26)
184 #define POC_SD3_DAT4_33V BIT(25)
185 #define POC_SD3_DAT3_33V BIT(24)
186 #define POC_SD3_DAT2_33V BIT(23)
187 #define POC_SD3_DAT1_33V BIT(22)
188 #define POC_SD3_DAT0_33V BIT(21)
189 #define POC_SD3_CMD_33V BIT(20)
190 #define POC_SD3_CLK_33V BIT(19)
191 #define POC_SD2_DS_33V BIT(18)
192 #define POC_SD2_DAT3_33V BIT(17)
193 #define POC_SD2_DAT2_33V BIT(16)
194 #define POC_SD2_DAT1_33V BIT(15)
195 #define POC_SD2_DAT0_33V BIT(14)
196 #define POC_SD2_CMD_33V BIT(13)
197 #define POC_SD2_CLK_33V BIT(12)
198 #define POC_SD1_DAT3_33V BIT(11)
199 #define POC_SD1_DAT2_33V BIT(10)
200 #define POC_SD1_DAT1_33V BIT(9)
201 #define POC_SD1_DAT0_33V BIT(8)
202 #define POC_SD1_CMD_33V BIT(7)
203 #define POC_SD1_CLK_33V BIT(6)
204 #define POC_SD0_DAT3_33V BIT(5)
205 #define POC_SD0_DAT2_33V BIT(4)
206 #define POC_SD0_DAT1_33V BIT(3)
207 #define POC_SD0_DAT0_33V BIT(2)
208 #define POC_SD0_CMD_33V BIT(1)
209 #define POC_SD0_CLK_33V BIT(0)
210
211 #define DRVCTRL0_MASK (0xCCCCCCCCU)
212 #define DRVCTRL1_MASK (0xCCCCCCC8U)
213 #define DRVCTRL2_MASK (0x88888888U)
214 #define DRVCTRL3_MASK (0x88888888U)
215 #define DRVCTRL4_MASK (0x88888888U)
216 #define DRVCTRL5_MASK (0x88888888U)
217 #define DRVCTRL6_MASK (0x88888888U)
218 #define DRVCTRL7_MASK (0x88888888U)
219 #define DRVCTRL8_MASK (0x88888888U)
220 #define DRVCTRL9_MASK (0x88888888U)
221 #define DRVCTRL10_MASK (0x88888888U)
222 #define DRVCTRL11_MASK (0x888888CCU)
223 #define DRVCTRL12_MASK (0xCCCFFFCFU)
224 #define DRVCTRL13_MASK (0xCC888888U)
225 #define DRVCTRL14_MASK (0x88888888U)
226 #define DRVCTRL15_MASK (0x88888888U)
227 #define DRVCTRL16_MASK (0x88888888U)
228 #define DRVCTRL17_MASK (0x88888888U)
229 #define DRVCTRL18_MASK (0x88888888U)
230 #define DRVCTRL19_MASK (0x88888888U)
231 #define DRVCTRL20_MASK (0x88888888U)
232 #define DRVCTRL21_MASK (0x88888888U)
233 #define DRVCTRL22_MASK (0x88888888U)
234 #define DRVCTRL23_MASK (0x88888888U)
235 #define DRVCTRL24_MASK (0x8888888FU)
236
237 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
238 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
239 #define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
240 #define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
241 #define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
242 #define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
243 #define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
244 #define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
245 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
246 #define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
247 #define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
248 #define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
249 #define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
250 #define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
251 #define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
252 #define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
253 #define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
254 #define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
255 #define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
256 #define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
257 #define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
258 #define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
259 #define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
260 #define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
261 #define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
262 #define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
263 #define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
264 #define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
265 #define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
266 #define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
267 #define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
268 #define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
269 #define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
270 #define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
271 #define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
272 #define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
273 #define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
274 #define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
275 #define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
276 #define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
277 #define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
278 #define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
279 #define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
280 #define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
281 #define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
284 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
285 #define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
286 #define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
287 #define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
288 #define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
289 #define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
290 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
291 #define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
292 #define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
293 #define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
294 #define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
295 #define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
296 #define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
297 #define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
298 #define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
299 #define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
300 #define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
301 #define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
302 #define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
303 #define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
304 #define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
305 #define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
306 #define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
307 #define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
308 #define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
309 #define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
310 #define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
311 #define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
312 #define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
313 #define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
314 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
315 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
316 #define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
317 #define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
318 #define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
319 #define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
320 #define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
321 #define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
322 #define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
323 #define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
324 #define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
325 #define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
326 #define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
327 #define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
328 #define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
329 #define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
330 #define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
331 #define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
332 #define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
333 #define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
334 #define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
335 #define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
336 #define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
337 #define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
338 #define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
339 #define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
340 #define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
341 #define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
342 #define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
343 #define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
344 #define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
345 #define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
346 #define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
347 #define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
348 #define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
349 #define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
350 #define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
351 #define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
352 #define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
353 #define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
354 #define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
355 #define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
356 #define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
357 #define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
358 #define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
359 #define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
360 #define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
361 #define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
362 #define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
363 #define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
364 #define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
365 #define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
366 #define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
367 #define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
368 #define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
369 #define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
370 #define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
371 #define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
372 #define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
373 #define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
374 #define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
375 #define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
376 #define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
377 #define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
378 #define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
379 #define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
380 #define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
381 #define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
382 #define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
383 #define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
384 #define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
385 #define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
386 #define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
387 #define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
388 #define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
389 #define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
390 #define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
391 #define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
392 #define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
393 #define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
394 #define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
395 #define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
396 #define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
397 #define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
398 #define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
399 #define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
400 #define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
401 #define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
402 #define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
403 #define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
404 #define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
405 #define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
406 #define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
407 #define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
408 #define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
409 #define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
410 #define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
411 #define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
412 #define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
413 #define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
414 #define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
415 #define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
416 #define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
417 #define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
418 #define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
419 #define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
420 #define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
421 #define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
422 #define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
423 #define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
424 #define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
425 #define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
426 #define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
427 #define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
428 #define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
429 #define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
430 #define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
431 #define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
432
433 #define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
434 #define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
435 #define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
436 #define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
437 #define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
438 #define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
439 #define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
440 #define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
441 #define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
442 #define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
443 #define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
444 #define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
445 #define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
446 #define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
447 #define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
448 #define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
449 #define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
450 #define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
451 #define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
452 #define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
453 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
454 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
455 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
456 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
457 #define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
458 #define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
459 #define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
460 #define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
461 #define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
462 #define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
463 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
464 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
465 #define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
466 #define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
467 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
468 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
469 #define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
470 #define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
471 #define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
472 #define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
473 #define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
474 #define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
475 #define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
476 #define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
477 #define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
478 #define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
479 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
480 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
481 #define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
482 #define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
483 #define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
484 #define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
485 #define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
486 #define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
487 #define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
488 #define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
489 #define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
490 #define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
491 #define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
492 #define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
493 #define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
494 #define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
495 #define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
496 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
497 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
498 #define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
499 #define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
500 #define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
501 #define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
502 #define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
503 #define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
504 #define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
505 #define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
506 #define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
507 #define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
508 #define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
509 #define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
510 #define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
511 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
512 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
513 #define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
514 #define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
515 #define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
516 #define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
517 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
518 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
519 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
520 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
521 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
522 #define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
523 #define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
524 #define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
525 #define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
526 #define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
527 #define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
528 #define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
529 #define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
530 #define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
531 #define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
532 #define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
533 #define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
534 #define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
535 #define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
536 #define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
537 #define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
538 #define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
539 #define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
540 #define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
541 #define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
542 #define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
543 #define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
544 #define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
545 #define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
546 #define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
547 #define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
548 #define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
549 #define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
550 #define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
551 #define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
552 #define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
553 #define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
554 #define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
555 #define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
556 #define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
557 #define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
558 #define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
559 #define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
560 #define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
561 #define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
562 #define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
563 #define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
564 #define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
565 #define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
566 #define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
567 #define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
568 #define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
569 #define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
570 #define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
571 #define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
572 #define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
573
574 /* SCIF3 Registers for Dummy write */
575 #define SCIF3_BASE (0xE6C50000U)
576 #define SCIF3_SCFCR (SCIF3_BASE + 0x0018U)
577 #define SCIF3_SCFDR (SCIF3_BASE + 0x001CU)
578 #define SCFCR_DATA (0x0000U)
579
580 /* Realtime module stop control */
581 #define CPG_BASE (0xE6150000U)
582 #define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U)
583 #define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
584 #define SCMSTPCR0_RTDMAC (0x00200000U)
585
586 /* RT-DMAC Registers */
587 #define RTDMAC_CH (0U) /* choose 0 to 15 */
588
589 #define RTDMAC_BASE (0xFFC10000U)
590 #define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U)
591 #define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U)
592 #define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x)))
593 #define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x)))
594 #define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x)))
595 #define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x)))
596 #define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x)))
597 #define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x)))
598 #define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U)
599 #define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U)
600 #define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U)
601 #define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U)
602
603 #define RDMOR_DME (0x0001U) /* DMA Master Enable */
604 #define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */
605 #define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */
606 #define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */
607 #define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */
608 #define RDMCHCR_DE (0x00000001U) /* DMA Enable */
609 #define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */
610 #define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */
611 #define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */
612
start_rtdma0_descriptor(void)613 static void start_rtdma0_descriptor(void)
614 {
615 uint32_t reg;
616
617 reg = mmio_read_32(RCAR_PRR);
618 reg &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
619 if (reg == (PRR_PRODUCT_M3_CUT10)) {
620 /* Enable clock supply to RTDMAC. */
621 mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
622
623 /* Initialize ch0, Reset Descriptor */
624 mmio_write_32(RTDMAC_RDMCHCLR, BIT(RTDMAC_CH));
625 mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
626
627 /* Enable DMA */
628 mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
629
630 /* Set first transfer */
631 mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
632 mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
633 mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
634
635 /* Set descriptor */
636 mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
637 mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
638 mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
639 mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
640 mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
641 | RDMDPBASE_SEL_EXT);
642
643 /* Set transfer parameter, Start transfer */
644 mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
645 | RDMCHCR_RPT_TCR
646 | RDMCHCR_TS_2
647 | RDMCHCR_RS_AUTO
648 | RDMCHCR_DE);
649 }
650 }
651
pfc_reg_write(uint32_t addr,uint32_t data)652 static void pfc_reg_write(uint32_t addr, uint32_t data)
653 {
654 uint32_t prr;
655
656 prr = mmio_read_32(RCAR_PRR);
657 prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
658
659 mmio_write_32(PFC_PMMR, ~data);
660 if (prr == (PRR_PRODUCT_M3_CUT10)) {
661 mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
662 }
663 mmio_write_32((uintptr_t)addr, data);
664 if (prr == (PRR_PRODUCT_M3_CUT10)) {
665 mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
666 }
667 }
668
pfc_init_g2m(void)669 void pfc_init_g2m(void)
670 {
671 uint32_t reg;
672
673 /*
674 * PFC write access problem seen on older SoC's. Added a workaround
675 * in RT-DMAC for fixing the same.
676 */
677 start_rtdma0_descriptor();
678
679 /* initialize module select */
680 pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
681 | MOD_SEL0_MSIOF2_A
682 | MOD_SEL0_MSIOF1_A
683 | MOD_SEL0_LBSC_A
684 | MOD_SEL0_IEBUS_A
685 | MOD_SEL0_I2C2_A
686 | MOD_SEL0_I2C1_A
687 | MOD_SEL0_HSCIF4_A
688 | MOD_SEL0_HSCIF3_A
689 | MOD_SEL0_HSCIF1_A
690 | MOD_SEL0_FSO_A
691 | MOD_SEL0_HSCIF2_A
692 | MOD_SEL0_ETHERAVB_A
693 | MOD_SEL0_DRIF3_A
694 | MOD_SEL0_DRIF2_A
695 | MOD_SEL0_DRIF1_A
696 | MOD_SEL0_DRIF0_A
697 | MOD_SEL0_CANFD0_A
698 | MOD_SEL0_ADG_A_A);
699 pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
700 | MOD_SEL1_TSIF0_A
701 | MOD_SEL1_TIMER_TMU_A
702 | MOD_SEL1_SSP1_1_A
703 | MOD_SEL1_SSP1_0_A
704 | MOD_SEL1_SSI_A
705 | MOD_SEL1_SPEED_PULSE_IF_A
706 | MOD_SEL1_SIMCARD_A
707 | MOD_SEL1_SDHI2_A
708 | MOD_SEL1_SCIF4_A
709 | MOD_SEL1_SCIF3_A
710 | MOD_SEL1_SCIF2_A
711 | MOD_SEL1_SCIF1_A
712 | MOD_SEL1_SCIF_A
713 | MOD_SEL1_REMOCON_A
714 | MOD_SEL1_RCAN0_A
715 | MOD_SEL1_PWM6_A
716 | MOD_SEL1_PWM5_A
717 | MOD_SEL1_PWM4_A
718 | MOD_SEL1_PWM3_A
719 | MOD_SEL1_PWM2_A
720 | MOD_SEL1_PWM1_A);
721 pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_B
722 | MOD_SEL2_I2C_3_B
723 | MOD_SEL2_I2C_0_B
724 | MOD_SEL2_FM_A
725 | MOD_SEL2_SCIF5_A
726 | MOD_SEL2_I2C6_A
727 | MOD_SEL2_NDF_A
728 | MOD_SEL2_SSI2_A
729 | MOD_SEL2_SSI9_A
730 | MOD_SEL2_TIMER_TMU2_A
731 | MOD_SEL2_ADG_B_A
732 | MOD_SEL2_ADG_C_A
733 | MOD_SEL2_VIN4_A);
734
735 /* initialize peripheral function select */
736 pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
737 | IPSR_24_FUNC(0)
738 | IPSR_20_FUNC(0)
739 | IPSR_16_FUNC(0)
740 | IPSR_12_FUNC(0)
741 | IPSR_8_FUNC(0)
742 | IPSR_4_FUNC(0)
743 | IPSR_0_FUNC(0));
744 pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
745 | IPSR_24_FUNC(0)
746 | IPSR_20_FUNC(0)
747 | IPSR_16_FUNC(0)
748 | IPSR_12_FUNC(3)
749 | IPSR_8_FUNC(3)
750 | IPSR_4_FUNC(3)
751 | IPSR_0_FUNC(3));
752 pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
753 | IPSR_24_FUNC(6)
754 | IPSR_20_FUNC(6)
755 | IPSR_16_FUNC(6)
756 | IPSR_12_FUNC(6)
757 | IPSR_8_FUNC(6)
758 | IPSR_4_FUNC(6)
759 | IPSR_0_FUNC(6));
760 pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
761 | IPSR_24_FUNC(6)
762 | IPSR_20_FUNC(6)
763 | IPSR_16_FUNC(6)
764 | IPSR_12_FUNC(6)
765 | IPSR_8_FUNC(0)
766 | IPSR_4_FUNC(0)
767 | IPSR_0_FUNC(0));
768 pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
769 | IPSR_24_FUNC(0)
770 | IPSR_20_FUNC(0)
771 | IPSR_16_FUNC(0)
772 | IPSR_12_FUNC(0)
773 | IPSR_8_FUNC(6)
774 | IPSR_4_FUNC(6)
775 | IPSR_0_FUNC(6));
776 pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
777 | IPSR_24_FUNC(0)
778 | IPSR_20_FUNC(0)
779 | IPSR_16_FUNC(0)
780 | IPSR_12_FUNC(0)
781 | IPSR_8_FUNC(6)
782 | IPSR_4_FUNC(0)
783 | IPSR_0_FUNC(0));
784 pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
785 | IPSR_24_FUNC(6)
786 | IPSR_20_FUNC(6)
787 | IPSR_16_FUNC(6)
788 | IPSR_12_FUNC(6)
789 | IPSR_8_FUNC(0)
790 | IPSR_4_FUNC(0)
791 | IPSR_0_FUNC(0));
792 pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
793 | IPSR_24_FUNC(0)
794 | IPSR_20_FUNC(0)
795 | IPSR_16_FUNC(0)
796 | IPSR_12_FUNC(0)
797 | IPSR_8_FUNC(6)
798 | IPSR_4_FUNC(6)
799 | IPSR_0_FUNC(6));
800 pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
801 | IPSR_24_FUNC(1)
802 | IPSR_20_FUNC(1)
803 | IPSR_16_FUNC(1)
804 | IPSR_12_FUNC(0)
805 | IPSR_8_FUNC(0)
806 | IPSR_4_FUNC(0)
807 | IPSR_0_FUNC(0));
808 pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
809 | IPSR_24_FUNC(0)
810 | IPSR_20_FUNC(0)
811 | IPSR_16_FUNC(0)
812 | IPSR_12_FUNC(0)
813 | IPSR_8_FUNC(0)
814 | IPSR_4_FUNC(0)
815 | IPSR_0_FUNC(0));
816 pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)
817 | IPSR_24_FUNC(0)
818 | IPSR_20_FUNC(0)
819 | IPSR_16_FUNC(0)
820 | IPSR_12_FUNC(0)
821 | IPSR_8_FUNC(0)
822 | IPSR_4_FUNC(0)
823 | IPSR_0_FUNC(0));
824 pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
825 | IPSR_24_FUNC(4)
826 | IPSR_20_FUNC(0)
827 | IPSR_16_FUNC(0)
828 | IPSR_12_FUNC(0)
829 | IPSR_8_FUNC(0)
830 | IPSR_4_FUNC(0)
831 | IPSR_0_FUNC(0));
832 pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
833 | IPSR_24_FUNC(0)
834 | IPSR_20_FUNC(0)
835 | IPSR_16_FUNC(0)
836 | IPSR_12_FUNC(0)
837 | IPSR_8_FUNC(4)
838 | IPSR_4_FUNC(0)
839 | IPSR_0_FUNC(0));
840 pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
841 | IPSR_24_FUNC(0)
842 | IPSR_20_FUNC(0)
843 | IPSR_16_FUNC(0)
844 | IPSR_12_FUNC(0)
845 | IPSR_8_FUNC(3)
846 | IPSR_4_FUNC(0)
847 | IPSR_0_FUNC(0));
848 pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
849 | IPSR_24_FUNC(0)
850 | IPSR_20_FUNC(0)
851 | IPSR_16_FUNC(0)
852 | IPSR_12_FUNC(0)
853 | IPSR_8_FUNC(0)
854 | IPSR_4_FUNC(3)
855 | IPSR_0_FUNC(8));
856 pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
857 | IPSR_24_FUNC(0)
858 | IPSR_20_FUNC(0)
859 | IPSR_16_FUNC(0)
860 | IPSR_12_FUNC(0)
861 | IPSR_8_FUNC(0)
862 | IPSR_4_FUNC(0)
863 | IPSR_0_FUNC(0));
864 pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
865 | IPSR_24_FUNC(0)
866 | IPSR_20_FUNC(0)
867 | IPSR_16_FUNC(0)
868 | IPSR_12_FUNC(0)
869 | IPSR_8_FUNC(0)
870 | IPSR_4_FUNC(0)
871 | IPSR_0_FUNC(0));
872 pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
873 | IPSR_24_FUNC(0)
874 | IPSR_20_FUNC(0)
875 | IPSR_16_FUNC(0)
876 | IPSR_12_FUNC(0)
877 | IPSR_8_FUNC(0)
878 | IPSR_4_FUNC(1)
879 | IPSR_0_FUNC(0));
880 pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
881 | IPSR_0_FUNC(0));
882
883 /* initialize GPIO/perihperal function select */
884 pfc_reg_write(PFC_GPSR0, GPSR0_D15
885 | GPSR0_D14
886 | GPSR0_D13
887 | GPSR0_D12
888 | GPSR0_D11
889 | GPSR0_D10
890 | GPSR0_D9
891 | GPSR0_D8
892 | GPSR0_D7
893 | GPSR0_D6
894 | GPSR0_D5
895 | GPSR0_D4
896 | GPSR0_D3
897 | GPSR0_D2
898 | GPSR0_D0);
899 pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
900 | GPSR1_EX_WAIT0_A
901 | GPSR1_WE1
902 | GPSR1_RD
903 | GPSR1_RD_WR
904 | GPSR1_CS0
905 | GPSR1_A19
906 | GPSR1_A18
907 | GPSR1_A17
908 | GPSR1_A16
909 | GPSR1_A15
910 | GPSR1_A14
911 | GPSR1_A13
912 | GPSR1_A12
913 | GPSR1_A7
914 | GPSR1_A6
915 | GPSR1_A5
916 | GPSR1_A4
917 | GPSR1_A3
918 | GPSR1_A2
919 | GPSR1_A1
920 | GPSR1_A0);
921 pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
922 | GPSR2_AVB_AVTP_MATCH_A
923 | GPSR2_AVB_LINK
924 | GPSR2_AVB_PHY_INT
925 | GPSR2_AVB_MDC
926 | GPSR2_PWM2_A
927 | GPSR2_PWM1_A
928 | GPSR2_IRQ4
929 | GPSR2_IRQ3
930 | GPSR2_IRQ2
931 | GPSR2_IRQ1
932 | GPSR2_IRQ0);
933 pfc_reg_write(PFC_GPSR3, GPSR3_SD0_CD
934 | GPSR3_SD1_DAT3
935 | GPSR3_SD1_DAT2
936 | GPSR3_SD1_DAT1
937 | GPSR3_SD1_DAT0
938 | GPSR3_SD0_DAT3
939 | GPSR3_SD0_DAT2
940 | GPSR3_SD0_DAT1
941 | GPSR3_SD0_DAT0
942 | GPSR3_SD0_CMD
943 | GPSR3_SD0_CLK);
944 pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
945 | GPSR4_SD3_DAT7
946 | GPSR4_SD3_DAT6
947 | GPSR4_SD3_DAT5
948 | GPSR4_SD3_DAT4
949 | GPSR4_SD3_DAT3
950 | GPSR4_SD3_DAT2
951 | GPSR4_SD3_DAT1
952 | GPSR4_SD3_DAT0
953 | GPSR4_SD3_CMD
954 | GPSR4_SD3_CLK
955 | GPSR4_SD2_DAT3
956 | GPSR4_SD2_DAT2
957 | GPSR4_SD2_DAT1
958 | GPSR4_SD2_DAT0
959 | GPSR4_SD2_CMD
960 | GPSR4_SD2_CLK);
961 pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_RXD
962 | GPSR5_MSIOF0_TXD
963 | GPSR5_MSIOF0_SYNC
964 | GPSR5_MSIOF0_SCK
965 | GPSR5_RX2_A
966 | GPSR5_TX2_A
967 | GPSR5_RTS1
968 | GPSR5_CTS1
969 | GPSR5_TX1_A
970 | GPSR5_RX1_A
971 | GPSR5_RTS0
972 | GPSR5_SCK0);
973 pfc_reg_write(PFC_GPSR6, GPSR6_AUDIO_CLKB_B
974 | GPSR6_AUDIO_CLKA_A
975 | GPSR6_SSI_WS6
976 | GPSR6_SSI_SCK6
977 | GPSR6_SSI_SDATA4
978 | GPSR6_SSI_WS4
979 | GPSR6_SSI_SCK4
980 | GPSR6_SSI_SDATA1_A
981 | GPSR6_SSI_SDATA0
982 | GPSR6_SSI_WS0129
983 | GPSR6_SSI_SCK0129);
984 pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
985 | GPSR7_AVS1);
986
987 /* initialize POC control register */
988 pfc_reg_write(PFC_POCCTRL0, POC_SD0_DAT3_33V
989 | POC_SD0_DAT2_33V
990 | POC_SD0_DAT1_33V
991 | POC_SD0_DAT0_33V
992 | POC_SD0_CMD_33V
993 | POC_SD0_CLK_33V);
994
995 /* initialize DRV control register */
996 reg = mmio_read_32(PFC_DRVCTRL0);
997 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
998 | DRVCTRL0_QSPI0_MOSI_IO0(3)
999 | DRVCTRL0_QSPI0_MISO_IO1(3)
1000 | DRVCTRL0_QSPI0_IO2(3)
1001 | DRVCTRL0_QSPI0_IO3(3)
1002 | DRVCTRL0_QSPI0_SSL(3)
1003 | DRVCTRL0_QSPI1_SPCLK(3)
1004 | DRVCTRL0_QSPI1_MOSI_IO0(3));
1005 pfc_reg_write(PFC_DRVCTRL0, reg);
1006 reg = mmio_read_32(PFC_DRVCTRL1);
1007 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
1008 | DRVCTRL1_QSPI1_IO2(3)
1009 | DRVCTRL1_QSPI1_IO3(3)
1010 | DRVCTRL1_QSPI1_SS(3)
1011 | DRVCTRL1_RPC_INT(3)
1012 | DRVCTRL1_RPC_WP(3)
1013 | DRVCTRL1_RPC_RESET(3)
1014 | DRVCTRL1_AVB_RX_CTL(7));
1015 pfc_reg_write(PFC_DRVCTRL1, reg);
1016 reg = mmio_read_32(PFC_DRVCTRL2);
1017 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
1018 | DRVCTRL2_AVB_RD0(7)
1019 | DRVCTRL2_AVB_RD1(7)
1020 | DRVCTRL2_AVB_RD2(7)
1021 | DRVCTRL2_AVB_RD3(7)
1022 | DRVCTRL2_AVB_TX_CTL(3)
1023 | DRVCTRL2_AVB_TXC(3)
1024 | DRVCTRL2_AVB_TD0(3));
1025 pfc_reg_write(PFC_DRVCTRL2, reg);
1026 reg = mmio_read_32(PFC_DRVCTRL3);
1027 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
1028 | DRVCTRL3_AVB_TD2(3)
1029 | DRVCTRL3_AVB_TD3(3)
1030 | DRVCTRL3_AVB_TXCREFCLK(7)
1031 | DRVCTRL3_AVB_MDIO(7)
1032 | DRVCTRL3_AVB_MDC(7)
1033 | DRVCTRL3_AVB_MAGIC(7)
1034 | DRVCTRL3_AVB_PHY_INT(7));
1035 pfc_reg_write(PFC_DRVCTRL3, reg);
1036 reg = mmio_read_32(PFC_DRVCTRL4);
1037 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
1038 | DRVCTRL4_AVB_AVTP_MATCH(7)
1039 | DRVCTRL4_AVB_AVTP_CAPTURE(7)
1040 | DRVCTRL4_IRQ0(7)
1041 | DRVCTRL4_IRQ1(7)
1042 | DRVCTRL4_IRQ2(7)
1043 | DRVCTRL4_IRQ3(7)
1044 | DRVCTRL4_IRQ4(7));
1045 pfc_reg_write(PFC_DRVCTRL4, reg);
1046 reg = mmio_read_32(PFC_DRVCTRL5);
1047 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
1048 | DRVCTRL5_PWM0(7)
1049 | DRVCTRL5_PWM1(7)
1050 | DRVCTRL5_PWM2(7)
1051 | DRVCTRL5_A0(3)
1052 | DRVCTRL5_A1(3)
1053 | DRVCTRL5_A2(3)
1054 | DRVCTRL5_A3(3));
1055 pfc_reg_write(PFC_DRVCTRL5, reg);
1056 reg = mmio_read_32(PFC_DRVCTRL6);
1057 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
1058 | DRVCTRL6_A5(3)
1059 | DRVCTRL6_A6(3)
1060 | DRVCTRL6_A7(3)
1061 | DRVCTRL6_A8(7)
1062 | DRVCTRL6_A9(7)
1063 | DRVCTRL6_A10(7)
1064 | DRVCTRL6_A11(7));
1065 pfc_reg_write(PFC_DRVCTRL6, reg);
1066 reg = mmio_read_32(PFC_DRVCTRL7);
1067 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
1068 | DRVCTRL7_A13(3)
1069 | DRVCTRL7_A14(3)
1070 | DRVCTRL7_A15(3)
1071 | DRVCTRL7_A16(3)
1072 | DRVCTRL7_A17(3)
1073 | DRVCTRL7_A18(3)
1074 | DRVCTRL7_A19(3));
1075 pfc_reg_write(PFC_DRVCTRL7, reg);
1076 reg = mmio_read_32(PFC_DRVCTRL8);
1077 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
1078 | DRVCTRL8_CS0(7)
1079 | DRVCTRL8_CS1_A2(7)
1080 | DRVCTRL8_BS(7)
1081 | DRVCTRL8_RD(7)
1082 | DRVCTRL8_RD_W(7)
1083 | DRVCTRL8_WE0(7)
1084 | DRVCTRL8_WE1(7));
1085 pfc_reg_write(PFC_DRVCTRL8, reg);
1086 reg = mmio_read_32(PFC_DRVCTRL9);
1087 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
1088 | DRVCTRL9_PRESETOU(7)
1089 | DRVCTRL9_D0(7)
1090 | DRVCTRL9_D1(7)
1091 | DRVCTRL9_D2(7)
1092 | DRVCTRL9_D3(7)
1093 | DRVCTRL9_D4(7)
1094 | DRVCTRL9_D5(7));
1095 pfc_reg_write(PFC_DRVCTRL9, reg);
1096 reg = mmio_read_32(PFC_DRVCTRL10);
1097 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
1098 | DRVCTRL10_D7(7)
1099 | DRVCTRL10_D8(3)
1100 | DRVCTRL10_D9(3)
1101 | DRVCTRL10_D10(3)
1102 | DRVCTRL10_D11(3)
1103 | DRVCTRL10_D12(3)
1104 | DRVCTRL10_D13(3));
1105 pfc_reg_write(PFC_DRVCTRL10, reg);
1106 reg = mmio_read_32(PFC_DRVCTRL11);
1107 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
1108 | DRVCTRL11_D15(3)
1109 | DRVCTRL11_AVS1(7)
1110 | DRVCTRL11_AVS2(7)
1111 | DRVCTRL11_GP7_02(7)
1112 | DRVCTRL11_GP7_03(7)
1113 | DRVCTRL11_DU_DOTCLKIN0(3)
1114 | DRVCTRL11_DU_DOTCLKIN1(3));
1115 pfc_reg_write(PFC_DRVCTRL11, reg);
1116 reg = mmio_read_32(PFC_DRVCTRL12);
1117 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
1118 | DRVCTRL12_DU_DOTCLKIN3(3)
1119 | DRVCTRL12_DU_FSCLKST(3)
1120 | DRVCTRL12_DU_TMS(3));
1121 pfc_reg_write(PFC_DRVCTRL12, reg);
1122 reg = mmio_read_32(PFC_DRVCTRL13);
1123 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
1124 | DRVCTRL13_ASEBRK(3)
1125 | DRVCTRL13_SD0_CLK(7)
1126 | DRVCTRL13_SD0_CMD(7)
1127 | DRVCTRL13_SD0_DAT0(7)
1128 | DRVCTRL13_SD0_DAT1(7)
1129 | DRVCTRL13_SD0_DAT2(7)
1130 | DRVCTRL13_SD0_DAT3(7));
1131 pfc_reg_write(PFC_DRVCTRL13, reg);
1132 reg = mmio_read_32(PFC_DRVCTRL14);
1133 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
1134 | DRVCTRL14_SD1_CMD(7)
1135 | DRVCTRL14_SD1_DAT0(5)
1136 | DRVCTRL14_SD1_DAT1(5)
1137 | DRVCTRL14_SD1_DAT2(5)
1138 | DRVCTRL14_SD1_DAT3(5)
1139 | DRVCTRL14_SD2_CLK(5)
1140 | DRVCTRL14_SD2_CMD(5));
1141 pfc_reg_write(PFC_DRVCTRL14, reg);
1142 reg = mmio_read_32(PFC_DRVCTRL15);
1143 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
1144 | DRVCTRL15_SD2_DAT1(5)
1145 | DRVCTRL15_SD2_DAT2(5)
1146 | DRVCTRL15_SD2_DAT3(5)
1147 | DRVCTRL15_SD2_DS(5)
1148 | DRVCTRL15_SD3_CLK(7)
1149 | DRVCTRL15_SD3_CMD(7)
1150 | DRVCTRL15_SD3_DAT0(7));
1151 pfc_reg_write(PFC_DRVCTRL15, reg);
1152 reg = mmio_read_32(PFC_DRVCTRL16);
1153 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
1154 | DRVCTRL16_SD3_DAT2(7)
1155 | DRVCTRL16_SD3_DAT3(7)
1156 | DRVCTRL16_SD3_DAT4(7)
1157 | DRVCTRL16_SD3_DAT5(7)
1158 | DRVCTRL16_SD3_DAT6(7)
1159 | DRVCTRL16_SD3_DAT7(7)
1160 | DRVCTRL16_SD3_DS(7));
1161 pfc_reg_write(PFC_DRVCTRL16, reg);
1162 reg = mmio_read_32(PFC_DRVCTRL17);
1163 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
1164 | DRVCTRL17_SD0_WP(7)
1165 | DRVCTRL17_SD1_CD(7)
1166 | DRVCTRL17_SD1_WP(7)
1167 | DRVCTRL17_SCK0(7)
1168 | DRVCTRL17_RX0(7)
1169 | DRVCTRL17_TX0(7)
1170 | DRVCTRL17_CTS0(7));
1171 pfc_reg_write(PFC_DRVCTRL17, reg);
1172 reg = mmio_read_32(PFC_DRVCTRL18);
1173 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
1174 | DRVCTRL18_RX1(7)
1175 | DRVCTRL18_TX1(7)
1176 | DRVCTRL18_CTS1(7)
1177 | DRVCTRL18_RTS1_TANS(7)
1178 | DRVCTRL18_SCK2(7)
1179 | DRVCTRL18_TX2(7)
1180 | DRVCTRL18_RX2(7));
1181 pfc_reg_write(PFC_DRVCTRL18, reg);
1182 reg = mmio_read_32(PFC_DRVCTRL19);
1183 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
1184 | DRVCTRL19_HRX0(7)
1185 | DRVCTRL19_HTX0(7)
1186 | DRVCTRL19_HCTS0(7)
1187 | DRVCTRL19_HRTS0(7)
1188 | DRVCTRL19_MSIOF0_SCK(7)
1189 | DRVCTRL19_MSIOF0_SYNC(7)
1190 | DRVCTRL19_MSIOF0_SS1(7));
1191 pfc_reg_write(PFC_DRVCTRL19, reg);
1192 reg = mmio_read_32(PFC_DRVCTRL20);
1193 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
1194 | DRVCTRL20_MSIOF0_SS2(7)
1195 | DRVCTRL20_MSIOF0_RXD(7)
1196 | DRVCTRL20_MLB_CLK(7)
1197 | DRVCTRL20_MLB_SIG(7)
1198 | DRVCTRL20_MLB_DAT(7)
1199 | DRVCTRL20_MLB_REF(7)
1200 | DRVCTRL20_SSI_SCK0129(7));
1201 pfc_reg_write(PFC_DRVCTRL20, reg);
1202 reg = mmio_read_32(PFC_DRVCTRL21);
1203 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
1204 | DRVCTRL21_SSI_SDATA0(7)
1205 | DRVCTRL21_SSI_SDATA1(7)
1206 | DRVCTRL21_SSI_SDATA2(7)
1207 | DRVCTRL21_SSI_SCK34(7)
1208 | DRVCTRL21_SSI_WS34(7)
1209 | DRVCTRL21_SSI_SDATA3(7)
1210 | DRVCTRL21_SSI_SCK4(7));
1211 pfc_reg_write(PFC_DRVCTRL21, reg);
1212 reg = mmio_read_32(PFC_DRVCTRL22);
1213 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
1214 | DRVCTRL22_SSI_SDATA4(7)
1215 | DRVCTRL22_SSI_SCK5(7)
1216 | DRVCTRL22_SSI_WS5(7)
1217 | DRVCTRL22_SSI_SDATA5(7)
1218 | DRVCTRL22_SSI_SCK6(7)
1219 | DRVCTRL22_SSI_WS6(7)
1220 | DRVCTRL22_SSI_SDATA6(7));
1221 pfc_reg_write(PFC_DRVCTRL22, reg);
1222 reg = mmio_read_32(PFC_DRVCTRL23);
1223 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
1224 | DRVCTRL23_SSI_WS78(7)
1225 | DRVCTRL23_SSI_SDATA7(7)
1226 | DRVCTRL23_SSI_SDATA8(7)
1227 | DRVCTRL23_SSI_SDATA9(7)
1228 | DRVCTRL23_AUDIO_CLKA(7)
1229 | DRVCTRL23_AUDIO_CLKB(7)
1230 | DRVCTRL23_USB0_PWEN(7));
1231 pfc_reg_write(PFC_DRVCTRL23, reg);
1232 reg = mmio_read_32(PFC_DRVCTRL24);
1233 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
1234 | DRVCTRL24_USB1_PWEN(7)
1235 | DRVCTRL24_USB1_OVC(7)
1236 | DRVCTRL24_USB30_PWEN(7)
1237 | DRVCTRL24_USB30_OVC(7)
1238 | DRVCTRL24_USB31_PWEN(7)
1239 | DRVCTRL24_USB31_OVC(7));
1240 pfc_reg_write(PFC_DRVCTRL24, reg);
1241
1242 /* initialize LSI pin pull-up/down control */
1243 pfc_reg_write(PFC_PUD0, 0x00005FBFU);
1244 pfc_reg_write(PFC_PUD1, 0x00300EFEU);
1245 pfc_reg_write(PFC_PUD2, 0x330001E6U);
1246 pfc_reg_write(PFC_PUD3, 0x000002E0U);
1247 pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
1248 pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
1249 pfc_reg_write(PFC_PUD6, 0x00000055U);
1250
1251 /* initialize LSI pin pull-enable register */
1252 pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
1253 pfc_reg_write(PFC_PUEN1, 0x00100234U);
1254 pfc_reg_write(PFC_PUEN2, 0x000004C4U);
1255 pfc_reg_write(PFC_PUEN3, 0x00000200U);
1256 pfc_reg_write(PFC_PUEN4, 0x3E000000U);
1257 pfc_reg_write(PFC_PUEN5, 0x1F000805U);
1258 pfc_reg_write(PFC_PUEN6, 0x00000006U);
1259
1260 /* initialize positive/negative logic select */
1261 mmio_write_32(GPIO_POSNEG0, 0x00000000U);
1262 mmio_write_32(GPIO_POSNEG1, 0x00000000U);
1263 mmio_write_32(GPIO_POSNEG2, 0x00000000U);
1264 mmio_write_32(GPIO_POSNEG3, 0x00000000U);
1265 mmio_write_32(GPIO_POSNEG4, 0x00000000U);
1266 mmio_write_32(GPIO_POSNEG5, 0x00000000U);
1267 mmio_write_32(GPIO_POSNEG6, 0x00000000U);
1268 mmio_write_32(GPIO_POSNEG7, 0x00000000U);
1269
1270 /* initialize general IO/interrupt switching */
1271 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
1272 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
1273 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
1274 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
1275 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
1276 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
1277 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
1278 mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
1279
1280 /* initialize general output register */
1281 mmio_write_32(GPIO_OUTDT0, 0x00000001U);
1282 mmio_write_32(GPIO_OUTDT1, 0x00000000U);
1283 mmio_write_32(GPIO_OUTDT2, 0x00000400U);
1284 mmio_write_32(GPIO_OUTDT3, 0x00000000U);
1285 mmio_write_32(GPIO_OUTDT4, 0x00000000U);
1286 mmio_write_32(GPIO_OUTDT5, 0x00000000U);
1287 mmio_write_32(GPIO_OUTDT6, 0x00003800U);
1288 mmio_write_32(GPIO_OUTDT7, 0x00000003U);
1289
1290 /* initialize general input/output switching */
1291 mmio_write_32(GPIO_INOUTSEL0, 0x00000001U);
1292 mmio_write_32(GPIO_INOUTSEL1, 0x00100B00U);
1293 mmio_write_32(GPIO_INOUTSEL2, 0x00000418U);
1294 mmio_write_32(GPIO_INOUTSEL3, 0x00002000U);
1295 mmio_write_32(GPIO_INOUTSEL4, 0x00000040U);
1296 mmio_write_32(GPIO_INOUTSEL5, 0x00000208U);
1297 mmio_write_32(GPIO_INOUTSEL6, 0x00013F00U);
1298 mmio_write_32(GPIO_INOUTSEL7, 0x00000003U);
1299
1300 }
1301
