1 /*
2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <common/interrupt_props.h>
13 #include <drivers/arm/gicv3.h>
14 #include <lib/spinlock.h>
15
16 #include "gicv3_private.h"
17
18 const gicv3_driver_data_t *gicv3_driver_data;
19
20 /*
21 * Spinlock to guard registers needing read-modify-write. APIs protected by this
22 * spinlock are used either at boot time (when only a single CPU is active), or
23 * when the system is fully coherent.
24 */
25 static spinlock_t gic_lock;
26
27 /*
28 * Redistributor power operations are weakly bound so that they can be
29 * overridden
30 */
31 #pragma weak gicv3_rdistif_off
32 #pragma weak gicv3_rdistif_on
33
34 /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */
35 static bool is_sgi_ppi(unsigned int id);
36
37 /*
38 * Helper macros to save and restore GICR and GICD registers
39 * corresponding to their numbers to and from the context
40 */
41 #define RESTORE_GICR_REG(base, ctx, name, i) \
42 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)])
43
44 #define SAVE_GICR_REG(base, ctx, name, i) \
45 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i))
46
47 /* Helper macros to save and restore GICD registers to and from the context */
48 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \
49 do { \
50 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\
51 int_id += (1U << REG##R_SHIFT)) { \
52 gicd_write_##reg((base), int_id, \
53 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \
54 REG##R_SHIFT]); \
55 } \
56 } while (false)
57
58 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \
59 do { \
60 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\
61 int_id += (1U << REG##R_SHIFT)) { \
62 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \
63 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \
64 } \
65 } while (false)
66
67 #if GIC_EXT_INTID
68 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \
69 do { \
70 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
71 int_id += (1U << REG##R_SHIFT)) { \
72 gicd_write_##reg((base), int_id, \
73 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
74 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
75 >> REG##R_SHIFT]); \
76 } \
77 } while (false)
78
79 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \
80 do { \
81 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
82 int_id += (1U << REG##R_SHIFT)) { \
83 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
84 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
85 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\
86 } \
87 } while (false)
88 #else
89 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG)
90 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG)
91 #endif /* GIC_EXT_INTID */
92
93 /*******************************************************************************
94 * This function initialises the ARM GICv3 driver in EL3 with provided platform
95 * inputs.
96 ******************************************************************************/
gicv3_driver_init(const gicv3_driver_data_t * plat_driver_data)97 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
98 {
99 unsigned int gic_version;
100 unsigned int gicv2_compat;
101
102 assert(plat_driver_data != NULL);
103 assert(plat_driver_data->gicd_base != 0U);
104 assert(plat_driver_data->rdistif_num != 0U);
105 assert(plat_driver_data->rdistif_base_addrs != NULL);
106
107 assert(IS_IN_EL3());
108
109 assert((plat_driver_data->interrupt_props_num != 0U) ?
110 (plat_driver_data->interrupt_props != NULL) : 1);
111
112 /* Check for system register support */
113 #ifndef __aarch64__
114 assert((read_id_pfr1() &
115 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
116 #else
117 assert((read_id_aa64pfr0_el1() &
118 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
119 #endif /* !__aarch64__ */
120
121 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
122 gic_version >>= PIDR2_ARCH_REV_SHIFT;
123 gic_version &= PIDR2_ARCH_REV_MASK;
124
125 /* Check GIC version */
126 #if !GIC_ENABLE_V4_EXTN
127 assert(gic_version == ARCH_REV_GICV3);
128 #endif
129 /*
130 * Find out whether the GIC supports the GICv2 compatibility mode.
131 * The ARE_S bit resets to 0 if supported
132 */
133 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
134 gicv2_compat >>= CTLR_ARE_S_SHIFT;
135 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK;
136
137 if (plat_driver_data->gicr_base != 0U) {
138 /*
139 * Find the base address of each implemented Redistributor interface.
140 * The number of interfaces should be equal to the number of CPUs in the
141 * system. The memory for saving these addresses has to be allocated by
142 * the platform port
143 */
144 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
145 plat_driver_data->rdistif_num,
146 plat_driver_data->gicr_base,
147 plat_driver_data->mpidr_to_core_pos);
148 #if !HW_ASSISTED_COHERENCY
149 /*
150 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
151 */
152 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs),
153 plat_driver_data->rdistif_num *
154 sizeof(*(plat_driver_data->rdistif_base_addrs)));
155 #endif
156 }
157 gicv3_driver_data = plat_driver_data;
158
159 /*
160 * The GIC driver data is initialized by the primary CPU with caches
161 * enabled. When the secondary CPU boots up, it initializes the
162 * GICC/GICR interface with the caches disabled. Hence flush the
163 * driver data to ensure coherency. This is not required if the
164 * platform has HW_ASSISTED_COHERENCY enabled.
165 */
166 #if !HW_ASSISTED_COHERENCY
167 flush_dcache_range((uintptr_t)&gicv3_driver_data,
168 sizeof(gicv3_driver_data));
169 flush_dcache_range((uintptr_t)gicv3_driver_data,
170 sizeof(*gicv3_driver_data));
171 #endif
172 gicv3_check_erratas_applies(plat_driver_data->gicd_base);
173
174 INFO("GICv%u with%s legacy support detected.\n", gic_version,
175 (gicv2_compat == 0U) ? "" : "out");
176 INFO("ARM GICv%u driver initialized in EL3\n", gic_version);
177 }
178
179 /*******************************************************************************
180 * This function initialises the GIC distributor interface based upon the data
181 * provided by the platform while initialising the driver.
182 ******************************************************************************/
gicv3_distif_init(void)183 void __init gicv3_distif_init(void)
184 {
185 unsigned int bitmap;
186
187 assert(gicv3_driver_data != NULL);
188 assert(gicv3_driver_data->gicd_base != 0U);
189
190 assert(IS_IN_EL3());
191
192 /*
193 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
194 * the ARE_S bit. The Distributor might generate a system error
195 * otherwise.
196 */
197 gicd_clr_ctlr(gicv3_driver_data->gicd_base,
198 CTLR_ENABLE_G0_BIT |
199 CTLR_ENABLE_G1S_BIT |
200 CTLR_ENABLE_G1NS_BIT,
201 RWP_TRUE);
202
203 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
204 gicd_set_ctlr(gicv3_driver_data->gicd_base,
205 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
206
207 /* Set the default attribute of all (E)SPIs */
208 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
209
210 bitmap = gicv3_secure_spis_config_props(
211 gicv3_driver_data->gicd_base,
212 gicv3_driver_data->interrupt_props,
213 gicv3_driver_data->interrupt_props_num);
214
215 /* Enable the secure (E)SPIs now that they have been configured */
216 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
217 }
218
219 /*******************************************************************************
220 * This function initialises the GIC Redistributor interface of the calling CPU
221 * (identified by the 'proc_num' parameter) based upon the data provided by the
222 * platform while initialising the driver.
223 ******************************************************************************/
gicv3_rdistif_init(unsigned int proc_num)224 void gicv3_rdistif_init(unsigned int proc_num)
225 {
226 uintptr_t gicr_base;
227 unsigned int bitmap;
228 uint32_t ctlr;
229
230 assert(gicv3_driver_data != NULL);
231 assert(proc_num < gicv3_driver_data->rdistif_num);
232 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
233 assert(gicv3_driver_data->gicd_base != 0U);
234
235 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base);
236 assert((ctlr & CTLR_ARE_S_BIT) != 0U);
237
238 assert(IS_IN_EL3());
239
240 /* Power on redistributor */
241 gicv3_rdistif_on(proc_num);
242
243 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
244 assert(gicr_base != 0U);
245
246 /* Set the default attribute of all SGIs and (E)PPIs */
247 gicv3_ppi_sgi_config_defaults(gicr_base);
248
249 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
250 gicv3_driver_data->interrupt_props,
251 gicv3_driver_data->interrupt_props_num);
252
253 /* Enable interrupt groups as required, if not already */
254 if ((ctlr & bitmap) != bitmap) {
255 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
256 }
257 }
258
259 /*******************************************************************************
260 * Functions to perform power operations on GIC Redistributor
261 ******************************************************************************/
gicv3_rdistif_off(unsigned int proc_num)262 void gicv3_rdistif_off(unsigned int proc_num)
263 {
264 }
265
gicv3_rdistif_on(unsigned int proc_num)266 void gicv3_rdistif_on(unsigned int proc_num)
267 {
268 }
269
270 /*******************************************************************************
271 * This function enables the GIC CPU interface of the calling CPU using only
272 * system register accesses.
273 ******************************************************************************/
gicv3_cpuif_enable(unsigned int proc_num)274 void gicv3_cpuif_enable(unsigned int proc_num)
275 {
276 uintptr_t gicr_base;
277 u_register_t scr_el3;
278 unsigned int icc_sre_el3;
279
280 assert(gicv3_driver_data != NULL);
281 assert(proc_num < gicv3_driver_data->rdistif_num);
282 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
283 assert(IS_IN_EL3());
284
285 /* Mark the connected core as awake */
286 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
287 gicv3_rdistif_mark_core_awake(gicr_base);
288
289 /* Disable the legacy interrupt bypass */
290 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT;
291
292 /*
293 * Enable system register access for EL3 and allow lower exception
294 * levels to configure the same for themselves. If the legacy mode is
295 * not supported, the SRE bit is RAO/WI
296 */
297 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
298 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
299
300 scr_el3 = read_scr_el3();
301
302 /*
303 * Switch to NS state to write Non secure ICC_SRE_EL1 and
304 * ICC_SRE_EL2 registers.
305 */
306 write_scr_el3(scr_el3 | SCR_NS_BIT);
307 isb();
308
309 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3);
310 write_icc_sre_el1(ICC_SRE_SRE_BIT);
311 isb();
312
313 /* Switch to secure state. */
314 write_scr_el3(scr_el3 & (~SCR_NS_BIT));
315 isb();
316
317 /* Write the secure ICC_SRE_EL1 register */
318 write_icc_sre_el1(ICC_SRE_SRE_BIT);
319 isb();
320
321 /* Program the idle priority in the PMR */
322 write_icc_pmr_el1(GIC_PRI_MASK);
323
324 /* Enable Group0 interrupts */
325 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT);
326
327 /* Enable Group1 Secure interrupts */
328 write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
329 IGRPEN1_EL3_ENABLE_G1S_BIT);
330 isb();
331 /* Add DSB to ensure visibility of System register writes */
332 dsb();
333 }
334
335 /*******************************************************************************
336 * This function disables the GIC CPU interface of the calling CPU using
337 * only system register accesses.
338 ******************************************************************************/
gicv3_cpuif_disable(unsigned int proc_num)339 void gicv3_cpuif_disable(unsigned int proc_num)
340 {
341 uintptr_t gicr_base;
342
343 assert(gicv3_driver_data != NULL);
344 assert(proc_num < gicv3_driver_data->rdistif_num);
345 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
346
347 assert(IS_IN_EL3());
348
349 /* Disable legacy interrupt bypass */
350 write_icc_sre_el3(read_icc_sre_el3() |
351 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT));
352
353 /* Disable Group0 interrupts */
354 write_icc_igrpen0_el1(read_icc_igrpen0_el1() &
355 ~IGRPEN1_EL1_ENABLE_G0_BIT);
356
357 /* Disable Group1 Secure and Non-Secure interrupts */
358 write_icc_igrpen1_el3(read_icc_igrpen1_el3() &
359 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT |
360 IGRPEN1_EL3_ENABLE_G1S_BIT));
361
362 /* Synchronise accesses to group enable registers */
363 isb();
364 /* Add DSB to ensure visibility of System register writes */
365 dsb();
366
367 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
368 assert(gicr_base != 0UL);
369
370 /*
371 * dsb() already issued previously after clearing the CPU group
372 * enabled, apply below workaround to toggle the "DPG*"
373 * bits of GICR_CTLR register for unblocking event.
374 */
375 gicv3_apply_errata_wa_2384374(gicr_base);
376
377 /* Mark the connected core as asleep */
378 gicv3_rdistif_mark_core_asleep(gicr_base);
379 }
380
381 /*******************************************************************************
382 * This function returns the id of the highest priority pending interrupt at
383 * the GIC cpu interface.
384 ******************************************************************************/
gicv3_get_pending_interrupt_id(void)385 unsigned int gicv3_get_pending_interrupt_id(void)
386 {
387 unsigned int id;
388
389 assert(IS_IN_EL3());
390 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
391
392 /*
393 * If the ID is special identifier corresponding to G1S or G1NS
394 * interrupt, then read the highest pending group 1 interrupt.
395 */
396 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) {
397 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
398 }
399
400 return id;
401 }
402
403 /*******************************************************************************
404 * This function returns the type of the highest priority pending interrupt at
405 * the GIC cpu interface. The return values can be one of the following :
406 * PENDING_G1S_INTID : The interrupt type is secure Group 1.
407 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1.
408 * 0 - 1019 : The interrupt type is secure Group 0.
409 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
410 * sufficient priority to be signaled
411 ******************************************************************************/
gicv3_get_pending_interrupt_type(void)412 unsigned int gicv3_get_pending_interrupt_type(void)
413 {
414 assert(IS_IN_EL3());
415 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
416 }
417
418 /*******************************************************************************
419 * This function returns the type of the interrupt id depending upon the group
420 * this interrupt has been configured under by the interrupt controller i.e.
421 * group0 or group1 Secure / Non Secure. The return value can be one of the
422 * following :
423 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
424 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
425 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
426 * interrupt.
427 ******************************************************************************/
gicv3_get_interrupt_type(unsigned int id,unsigned int proc_num)428 unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num)
429 {
430 unsigned int igroup, grpmodr;
431 uintptr_t gicr_base;
432
433 assert(IS_IN_EL3());
434 assert(gicv3_driver_data != NULL);
435
436 /* Ensure the parameters are valid */
437 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID));
438 assert(proc_num < gicv3_driver_data->rdistif_num);
439
440 /* All LPI interrupts are Group 1 non secure */
441 if (id >= MIN_LPI_ID) {
442 return INTR_GROUP1NS;
443 }
444
445 /* Check interrupt ID */
446 if (is_sgi_ppi(id)) {
447 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
448 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
449 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
450 igroup = gicr_get_igroupr(gicr_base, id);
451 grpmodr = gicr_get_igrpmodr(gicr_base, id);
452 } else {
453 /* SPIs: 32-1019, ESPIs: 4096-5119 */
454 assert(gicv3_driver_data->gicd_base != 0U);
455 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id);
456 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id);
457 }
458
459 /*
460 * If the IGROUP bit is set, then it is a Group 1 Non secure
461 * interrupt
462 */
463 if (igroup != 0U) {
464 return INTR_GROUP1NS;
465 }
466
467 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
468 if (grpmodr != 0U) {
469 return INTR_GROUP1S;
470 }
471
472 /* Else it is a Group 0 Secure interrupt */
473 return INTR_GROUP0;
474 }
475
476 /*****************************************************************************
477 * Function to save and disable the GIC ITS register context. The power
478 * management of GIC ITS is implementation-defined and this function doesn't
479 * save any memory structures required to support ITS. As the sequence to save
480 * this state is implementation defined, it should be executed in platform
481 * specific code. Calling this function alone and then powering down the GIC and
482 * ITS without implementing the aforementioned platform specific code will
483 * corrupt the ITS state.
484 *
485 * This function must be invoked after the GIC CPU interface is disabled.
486 *****************************************************************************/
gicv3_its_save_disable(uintptr_t gits_base,gicv3_its_ctx_t * const its_ctx)487 void gicv3_its_save_disable(uintptr_t gits_base,
488 gicv3_its_ctx_t * const its_ctx)
489 {
490 unsigned int i;
491
492 assert(gicv3_driver_data != NULL);
493 assert(IS_IN_EL3());
494 assert(its_ctx != NULL);
495 assert(gits_base != 0U);
496
497 its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
498
499 /* Disable the ITS */
500 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT);
501
502 /* Wait for quiescent state */
503 gits_wait_for_quiescent_bit(gits_base);
504
505 its_ctx->gits_cbaser = gits_read_cbaser(gits_base);
506 its_ctx->gits_cwriter = gits_read_cwriter(gits_base);
507
508 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) {
509 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i);
510 }
511 }
512
513 /*****************************************************************************
514 * Function to restore the GIC ITS register context. The power
515 * management of GIC ITS is implementation defined and this function doesn't
516 * restore any memory structures required to support ITS. The assumption is
517 * that these structures are in memory and are retained during system suspend.
518 *
519 * This must be invoked before the GIC CPU interface is enabled.
520 *****************************************************************************/
gicv3_its_restore(uintptr_t gits_base,const gicv3_its_ctx_t * const its_ctx)521 void gicv3_its_restore(uintptr_t gits_base,
522 const gicv3_its_ctx_t * const its_ctx)
523 {
524 unsigned int i;
525
526 assert(gicv3_driver_data != NULL);
527 assert(IS_IN_EL3());
528 assert(its_ctx != NULL);
529 assert(gits_base != 0U);
530
531 /* Assert that the GITS is disabled and quiescent */
532 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
533 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U);
534
535 gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
536 gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
537
538 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) {
539 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]);
540 }
541
542 /* Restore the ITS CTLR but leave the ITS disabled */
543 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT);
544 }
545
546 /*****************************************************************************
547 * Function to save the GIC Redistributor register context. This function
548 * must be invoked after CPU interface disable and prior to Distributor save.
549 *****************************************************************************/
gicv3_rdistif_save(unsigned int proc_num,gicv3_redist_ctx_t * const rdist_ctx)550 void gicv3_rdistif_save(unsigned int proc_num,
551 gicv3_redist_ctx_t * const rdist_ctx)
552 {
553 uintptr_t gicr_base;
554 unsigned int i, ppi_regs_num, regs_num;
555
556 assert(gicv3_driver_data != NULL);
557 assert(proc_num < gicv3_driver_data->rdistif_num);
558 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
559 assert(IS_IN_EL3());
560 assert(rdist_ctx != NULL);
561
562 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
563
564 #if GIC_EXT_INTID
565 /* Calculate number of PPI registers */
566 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
567 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
568 /* All other values except PPInum [0-2] are reserved */
569 if (ppi_regs_num > 3U) {
570 ppi_regs_num = 1U;
571 }
572 #else
573 ppi_regs_num = 1U;
574 #endif
575 /*
576 * Wait for any write to GICR_CTLR to complete before trying to save any
577 * state.
578 */
579 gicr_wait_for_pending_write(gicr_base);
580
581 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base);
582
583 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base);
584 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base);
585
586 /* 32 interrupt IDs per register */
587 for (i = 0U; i < ppi_regs_num; ++i) {
588 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i);
589 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i);
590 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i);
591 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i);
592 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i);
593 }
594
595 /* 16 interrupt IDs per GICR_ICFGR register */
596 regs_num = ppi_regs_num << 1;
597 for (i = 0U; i < regs_num; ++i) {
598 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i);
599 }
600
601 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
602
603 /* 4 interrupt IDs per GICR_IPRIORITYR register */
604 regs_num = ppi_regs_num << 3;
605 for (i = 0U; i < regs_num; ++i) {
606 rdist_ctx->gicr_ipriorityr[i] =
607 gicr_ipriorityr_read(gicr_base, i);
608 }
609
610 /*
611 * Call the pre-save hook that implements the IMP DEF sequence that may
612 * be required on some GIC implementations. As this may need to access
613 * the Redistributor registers, we pass it proc_num.
614 */
615 gicv3_distif_pre_save(proc_num);
616 }
617
618 /*****************************************************************************
619 * Function to restore the GIC Redistributor register context. We disable
620 * LPI and per-cpu interrupts before we start restore of the Redistributor.
621 * This function must be invoked after Distributor restore but prior to
622 * CPU interface enable. The pending and active interrupts are restored
623 * after the interrupts are fully configured and enabled.
624 *****************************************************************************/
gicv3_rdistif_init_restore(unsigned int proc_num,const gicv3_redist_ctx_t * const rdist_ctx)625 void gicv3_rdistif_init_restore(unsigned int proc_num,
626 const gicv3_redist_ctx_t * const rdist_ctx)
627 {
628 uintptr_t gicr_base;
629 unsigned int i, ppi_regs_num, regs_num;
630
631 assert(gicv3_driver_data != NULL);
632 assert(proc_num < gicv3_driver_data->rdistif_num);
633 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
634 assert(IS_IN_EL3());
635 assert(rdist_ctx != NULL);
636
637 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
638
639 #if GIC_EXT_INTID
640 /* Calculate number of PPI registers */
641 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
642 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
643 /* All other values except PPInum [0-2] are reserved */
644 if (ppi_regs_num > 3U) {
645 ppi_regs_num = 1U;
646 }
647 #else
648 ppi_regs_num = 1U;
649 #endif
650 /* Power on redistributor */
651 gicv3_rdistif_on(proc_num);
652
653 /*
654 * Call the post-restore hook that implements the IMP DEF sequence that
655 * may be required on some GIC implementations. As this may need to
656 * access the Redistributor registers, we pass it proc_num.
657 */
658 gicv3_distif_post_restore(proc_num);
659
660 /*
661 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them.
662 * This is a more scalable approach as it avoids clearing the enable
663 * bits in the GICD_CTLR.
664 */
665 for (i = 0U; i < ppi_regs_num; ++i) {
666 gicr_write_icenabler(gicr_base, i, ~0U);
667 }
668
669 /* Wait for pending writes to GICR_ICENABLER */
670 gicr_wait_for_pending_write(gicr_base);
671
672 /*
673 * Disable the LPIs to avoid unpredictable behavior when writing to
674 * GICR_PROPBASER and GICR_PENDBASER.
675 */
676 gicr_write_ctlr(gicr_base,
677 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT));
678
679 /* Restore registers' content */
680 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser);
681 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser);
682
683 /* 32 interrupt IDs per register */
684 for (i = 0U; i < ppi_regs_num; ++i) {
685 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i);
686 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i);
687 }
688
689 /* 4 interrupt IDs per GICR_IPRIORITYR register */
690 regs_num = ppi_regs_num << 3;
691 for (i = 0U; i < regs_num; ++i) {
692 gicr_ipriorityr_write(gicr_base, i,
693 rdist_ctx->gicr_ipriorityr[i]);
694 }
695
696 /* 16 interrupt IDs per GICR_ICFGR register */
697 regs_num = ppi_regs_num << 1;
698 for (i = 0U; i < regs_num; ++i) {
699 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i);
700 }
701
702 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr);
703
704 /* Restore after group and priorities are set.
705 * 32 interrupt IDs per register
706 */
707 for (i = 0U; i < ppi_regs_num; ++i) {
708 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i);
709 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i);
710 }
711
712 /*
713 * Wait for all writes to the Distributor to complete before enabling
714 * the SGI and (E)PPIs.
715 */
716 gicr_wait_for_upstream_pending_write(gicr_base);
717
718 /* 32 interrupt IDs per GICR_ISENABLER register */
719 for (i = 0U; i < ppi_regs_num; ++i) {
720 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i);
721 }
722
723 /*
724 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case
725 * the first write to GICR_CTLR was still in flight (this write only
726 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this
727 * bit).
728 */
729 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr);
730 gicr_wait_for_pending_write(gicr_base);
731 }
732
733 /*****************************************************************************
734 * Function to save the GIC Distributor register context. This function
735 * must be invoked after CPU interface disable and Redistributor save.
736 *****************************************************************************/
gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)737 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
738 {
739 assert(gicv3_driver_data != NULL);
740 assert(gicv3_driver_data->gicd_base != 0U);
741 assert(IS_IN_EL3());
742 assert(dist_ctx != NULL);
743
744 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
745 unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
746 #if GIC_EXT_INTID
747 unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
748 #endif
749
750 /* Wait for pending write to complete */
751 gicd_wait_for_pending_write(gicd_base);
752
753 /* Save the GICD_CTLR */
754 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base);
755
756 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */
757 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
758
759 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */
760 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP);
761
762 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */
763 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE);
764
765 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */
766 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE);
767
768 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */
769 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND);
770
771 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */
772 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND);
773
774 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */
775 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE);
776
777 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */
778 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE);
779
780 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */
781 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY);
782
783 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */
784 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY);
785
786 /* Save GICD_ICFGR for INTIDs 32 - 1019 */
787 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG);
788
789 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */
790 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG);
791
792 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */
793 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD);
794
795 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */
796 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD);
797
798 /* Save GICD_NSACR for INTIDs 32 - 1019 */
799 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC);
800
801 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */
802 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC);
803
804 /* Save GICD_IROUTER for INTIDs 32 - 1019 */
805 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE);
806
807 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */
808 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE);
809
810 /*
811 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when
812 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3
813 * driver.
814 */
815 }
816
817 /*****************************************************************************
818 * Function to restore the GIC Distributor register context. We disable G0, G1S
819 * and G1NS interrupt groups before we start restore of the Distributor. This
820 * function must be invoked prior to Redistributor restore and CPU interface
821 * enable. The pending and active interrupts are restored after the interrupts
822 * are fully configured and enabled.
823 *****************************************************************************/
gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)824 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
825 {
826 assert(gicv3_driver_data != NULL);
827 assert(gicv3_driver_data->gicd_base != 0U);
828 assert(IS_IN_EL3());
829 assert(dist_ctx != NULL);
830
831 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
832
833 /*
834 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
835 * the ARE_S bit. The Distributor might generate a system error
836 * otherwise.
837 */
838 gicd_clr_ctlr(gicd_base,
839 CTLR_ENABLE_G0_BIT |
840 CTLR_ENABLE_G1S_BIT |
841 CTLR_ENABLE_G1NS_BIT,
842 RWP_TRUE);
843
844 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
845 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
846
847 unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
848 #if GIC_EXT_INTID
849 unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
850 #endif
851 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
852 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
853
854 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */
855 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP);
856
857 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */
858 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY);
859
860 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */
861 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY);
862
863 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */
864 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG);
865
866 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */
867 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG);
868
869 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */
870 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD);
871
872 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */
873 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD);
874
875 /* Restore GICD_NSACR for INTIDs 32 - 1019 */
876 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC);
877
878 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */
879 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC);
880
881 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */
882 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE);
883
884 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */
885 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE);
886
887 /*
888 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after
889 * the interrupts are configured.
890 */
891
892 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */
893 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE);
894
895 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */
896 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE);
897
898 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */
899 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND);
900
901 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */
902 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND);
903
904 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */
905 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE);
906
907 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */
908 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE);
909
910 /* Restore the GICD_CTLR */
911 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr);
912 gicd_wait_for_pending_write(gicd_base);
913 }
914
915 /*******************************************************************************
916 * This function gets the priority of the interrupt the processor is currently
917 * servicing.
918 ******************************************************************************/
gicv3_get_running_priority(void)919 unsigned int gicv3_get_running_priority(void)
920 {
921 return (unsigned int)read_icc_rpr_el1();
922 }
923
924 /*******************************************************************************
925 * This function checks if the interrupt identified by id is active (whether the
926 * state is either active, or active and pending). The proc_num is used if the
927 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor
928 * interface.
929 ******************************************************************************/
gicv3_get_interrupt_active(unsigned int id,unsigned int proc_num)930 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
931 {
932 assert(gicv3_driver_data != NULL);
933 assert(gicv3_driver_data->gicd_base != 0U);
934 assert(proc_num < gicv3_driver_data->rdistif_num);
935 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
936
937 /* Check interrupt ID */
938 if (is_sgi_ppi(id)) {
939 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
940 return gicr_get_isactiver(
941 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
942 }
943
944 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
945 return gicd_get_isactiver(gicv3_driver_data->gicd_base, id);
946 }
947
948 /*******************************************************************************
949 * This function enables the interrupt identified by id. The proc_num
950 * is used if the interrupt is SGI or PPI, and programs the corresponding
951 * Redistributor interface.
952 ******************************************************************************/
gicv3_enable_interrupt(unsigned int id,unsigned int proc_num)953 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
954 {
955 assert(gicv3_driver_data != NULL);
956 assert(gicv3_driver_data->gicd_base != 0U);
957 assert(proc_num < gicv3_driver_data->rdistif_num);
958 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
959
960 /*
961 * Ensure that any shared variable updates depending on out of band
962 * interrupt trigger are observed before enabling interrupt.
963 */
964 dsbishst();
965
966 /* Check interrupt ID */
967 if (is_sgi_ppi(id)) {
968 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
969 gicr_set_isenabler(
970 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
971 } else {
972 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
973 gicd_set_isenabler(gicv3_driver_data->gicd_base, id);
974 }
975 }
976
977 /*******************************************************************************
978 * This function disables the interrupt identified by id. The proc_num
979 * is used if the interrupt is SGI or PPI, and programs the corresponding
980 * Redistributor interface.
981 ******************************************************************************/
gicv3_disable_interrupt(unsigned int id,unsigned int proc_num)982 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
983 {
984 assert(gicv3_driver_data != NULL);
985 assert(gicv3_driver_data->gicd_base != 0U);
986 assert(proc_num < gicv3_driver_data->rdistif_num);
987 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
988
989 /*
990 * Disable interrupt, and ensure that any shared variable updates
991 * depending on out of band interrupt trigger are observed afterwards.
992 */
993
994 /* Check interrupt ID */
995 if (is_sgi_ppi(id)) {
996 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
997 gicr_set_icenabler(
998 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
999
1000 /* Write to clear enable requires waiting for pending writes */
1001 gicr_wait_for_pending_write(
1002 gicv3_driver_data->rdistif_base_addrs[proc_num]);
1003 } else {
1004 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
1005 gicd_set_icenabler(gicv3_driver_data->gicd_base, id);
1006
1007 /* Write to clear enable requires waiting for pending writes */
1008 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base);
1009 }
1010
1011 dsbishst();
1012 }
1013
1014 /*******************************************************************************
1015 * This function sets the interrupt priority as supplied for the given interrupt
1016 * id.
1017 ******************************************************************************/
gicv3_set_interrupt_priority(unsigned int id,unsigned int proc_num,unsigned int priority)1018 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
1019 unsigned int priority)
1020 {
1021 uintptr_t gicr_base;
1022
1023 assert(gicv3_driver_data != NULL);
1024 assert(gicv3_driver_data->gicd_base != 0U);
1025 assert(proc_num < gicv3_driver_data->rdistif_num);
1026 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
1027
1028 /* Check interrupt ID */
1029 if (is_sgi_ppi(id)) {
1030 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1031 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
1032 gicr_set_ipriorityr(gicr_base, id, priority);
1033 } else {
1034 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
1035 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority);
1036 }
1037 }
1038
1039 /*******************************************************************************
1040 * This function assigns group for the interrupt identified by id. The proc_num
1041 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding
1042 * Redistributor interface. The group can be any of GICV3_INTR_GROUP*
1043 ******************************************************************************/
gicv3_set_interrupt_type(unsigned int id,unsigned int proc_num,unsigned int type)1044 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
1045 unsigned int type)
1046 {
1047 bool igroup = false, grpmod = false;
1048 uintptr_t gicr_base;
1049
1050 assert(gicv3_driver_data != NULL);
1051 assert(gicv3_driver_data->gicd_base != 0U);
1052 assert(proc_num < gicv3_driver_data->rdistif_num);
1053 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
1054
1055 switch (type) {
1056 case INTR_GROUP1S:
1057 igroup = false;
1058 grpmod = true;
1059 break;
1060 case INTR_GROUP0:
1061 igroup = false;
1062 grpmod = false;
1063 break;
1064 case INTR_GROUP1NS:
1065 igroup = true;
1066 grpmod = false;
1067 break;
1068 default:
1069 assert(false);
1070 break;
1071 }
1072
1073 /* Check interrupt ID */
1074 if (is_sgi_ppi(id)) {
1075 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1076 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
1077
1078 igroup ? gicr_set_igroupr(gicr_base, id) :
1079 gicr_clr_igroupr(gicr_base, id);
1080 grpmod ? gicr_set_igrpmodr(gicr_base, id) :
1081 gicr_clr_igrpmodr(gicr_base, id);
1082 } else {
1083 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
1084
1085 /* Serialize read-modify-write to Distributor registers */
1086 spin_lock(&gic_lock);
1087
1088 igroup ? gicd_set_igroupr(gicv3_driver_data->gicd_base, id) :
1089 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id);
1090 grpmod ? gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id) :
1091 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id);
1092
1093 spin_unlock(&gic_lock);
1094 }
1095 }
1096
1097 /*******************************************************************************
1098 * This function raises the specified Secure Group 0 SGI.
1099 *
1100 * The target parameter must be a valid MPIDR in the system.
1101 ******************************************************************************/
gicv3_raise_secure_g0_sgi(unsigned int sgi_num,u_register_t target)1102 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target)
1103 {
1104 unsigned int tgt, aff3, aff2, aff1, aff0;
1105 uint64_t sgi_val;
1106
1107 /* Verify interrupt number is in the SGI range */
1108 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID));
1109
1110 /* Extract affinity fields from target */
1111 aff0 = MPIDR_AFFLVL0_VAL(target);
1112 aff1 = MPIDR_AFFLVL1_VAL(target);
1113 aff2 = MPIDR_AFFLVL2_VAL(target);
1114 aff3 = MPIDR_AFFLVL3_VAL(target);
1115
1116 /*
1117 * Make target list from affinity 0, and ensure GICv3 SGI can target
1118 * this PE.
1119 */
1120 assert(aff0 < GICV3_MAX_SGI_TARGETS);
1121 tgt = BIT_32(aff0);
1122
1123 /* Raise SGI to PE specified by its affinity */
1124 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
1125 tgt);
1126
1127 /*
1128 * Ensure that any shared variable updates depending on out of band
1129 * interrupt trigger are observed before raising SGI.
1130 */
1131 dsbishst();
1132 write_icc_sgi0r_el1(sgi_val);
1133 isb();
1134 }
1135
1136 /*******************************************************************************
1137 * This function sets the interrupt routing for the given (E)SPI interrupt id.
1138 * The interrupt routing is specified in routing mode and mpidr.
1139 *
1140 * The routing mode can be either of:
1141 * - GICV3_IRM_ANY
1142 * - GICV3_IRM_PE
1143 *
1144 * The mpidr is the affinity of the PE to which the interrupt will be routed,
1145 * and is ignored for routing mode GICV3_IRM_ANY.
1146 ******************************************************************************/
gicv3_set_spi_routing(unsigned int id,unsigned int irm,u_register_t mpidr)1147 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr)
1148 {
1149 unsigned long long aff;
1150 uint64_t router;
1151
1152 assert(gicv3_driver_data != NULL);
1153 assert(gicv3_driver_data->gicd_base != 0U);
1154
1155 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
1156
1157 assert(IS_SPI(id));
1158
1159 aff = gicd_irouter_val_from_mpidr(mpidr, irm);
1160 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff);
1161
1162 /*
1163 * In implementations that do not require 1 of N distribution of SPIs,
1164 * IRM might be RAZ/WI. Read back and verify IRM bit.
1165 */
1166 if (irm == GICV3_IRM_ANY) {
1167 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id);
1168 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) {
1169 ERROR("GICv3 implementation doesn't support routing ANY\n");
1170 panic();
1171 }
1172 }
1173 }
1174
1175 /*******************************************************************************
1176 * This function clears the pending status of an interrupt identified by id.
1177 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the
1178 * corresponding Redistributor interface.
1179 ******************************************************************************/
gicv3_clear_interrupt_pending(unsigned int id,unsigned int proc_num)1180 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
1181 {
1182 assert(gicv3_driver_data != NULL);
1183 assert(gicv3_driver_data->gicd_base != 0U);
1184 assert(proc_num < gicv3_driver_data->rdistif_num);
1185 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
1186
1187 /*
1188 * Clear pending interrupt, and ensure that any shared variable updates
1189 * depending on out of band interrupt trigger are observed afterwards.
1190 */
1191
1192 /* Check interrupt ID */
1193 if (is_sgi_ppi(id)) {
1194 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1195 gicr_set_icpendr(
1196 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
1197 } else {
1198 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
1199 gicd_set_icpendr(gicv3_driver_data->gicd_base, id);
1200 }
1201
1202 dsbishst();
1203 }
1204
1205 /*******************************************************************************
1206 * This function sets the pending status of an interrupt identified by id.
1207 * The proc_num is used if the interrupt is SGI or PPI and programs the
1208 * corresponding Redistributor interface.
1209 ******************************************************************************/
gicv3_set_interrupt_pending(unsigned int id,unsigned int proc_num)1210 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
1211 {
1212 assert(gicv3_driver_data != NULL);
1213 assert(gicv3_driver_data->gicd_base != 0U);
1214 assert(proc_num < gicv3_driver_data->rdistif_num);
1215 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
1216
1217 /*
1218 * Ensure that any shared variable updates depending on out of band
1219 * interrupt trigger are observed before setting interrupt pending.
1220 */
1221 dsbishst();
1222
1223 /* Check interrupt ID */
1224 if (is_sgi_ppi(id)) {
1225 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1226 gicr_set_ispendr(
1227 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
1228 } else {
1229 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
1230 gicd_set_ispendr(gicv3_driver_data->gicd_base, id);
1231 }
1232 }
1233
1234 /*******************************************************************************
1235 * This function sets the PMR register with the supplied value. Returns the
1236 * original PMR.
1237 ******************************************************************************/
gicv3_set_pmr(unsigned int mask)1238 unsigned int gicv3_set_pmr(unsigned int mask)
1239 {
1240 unsigned int old_mask;
1241
1242 old_mask = (unsigned int)read_icc_pmr_el1();
1243
1244 /*
1245 * Order memory updates w.r.t. PMR write, and ensure they're visible
1246 * before potential out of band interrupt trigger because of PMR update.
1247 * PMR system register writes are self-synchronizing, so no ISB required
1248 * thereafter.
1249 */
1250 dsbishst();
1251 write_icc_pmr_el1(mask);
1252
1253 return old_mask;
1254 }
1255
1256 /*******************************************************************************
1257 * This function delegates the responsibility of discovering the corresponding
1258 * Redistributor frames to each CPU itself. It is a modified version of
1259 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform
1260 * unlike the previous way in which only the Primary CPU did the discovery of
1261 * all the Redistributor frames for every CPU. It also handles the scenario in
1262 * which the frames of various CPUs are not contiguous in physical memory.
1263 ******************************************************************************/
gicv3_rdistif_probe(const uintptr_t gicr_frame)1264 int gicv3_rdistif_probe(const uintptr_t gicr_frame)
1265 {
1266 u_register_t mpidr, mpidr_self;
1267 unsigned int proc_num;
1268 uint64_t typer_val;
1269 uintptr_t rdistif_base;
1270 bool gicr_frame_found = false;
1271
1272 assert(gicv3_driver_data->gicr_base == 0U);
1273
1274 /* Ensure this function is called with Data Cache enabled */
1275 #ifndef __aarch64__
1276 assert((read_sctlr() & SCTLR_C_BIT) != 0U);
1277 #else
1278 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
1279 #endif /* !__aarch64__ */
1280
1281 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
1282 rdistif_base = gicr_frame;
1283 do {
1284 typer_val = gicr_read_typer(rdistif_base);
1285 mpidr = mpidr_from_gicr_typer(typer_val);
1286 if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
1287 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
1288 } else {
1289 proc_num = (unsigned int)(typer_val >>
1290 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK;
1291 }
1292 if (mpidr == mpidr_self) {
1293 /* The base address doesn't need to be initialized on
1294 * every warm boot.
1295 */
1296 if (gicv3_driver_data->rdistif_base_addrs[proc_num]
1297 != 0U) {
1298 return 0;
1299 }
1300 gicv3_driver_data->rdistif_base_addrs[proc_num] =
1301 rdistif_base;
1302 gicr_frame_found = true;
1303 break;
1304 }
1305 rdistif_base += gicv3_redist_size(typer_val);
1306 } while ((typer_val & TYPER_LAST_BIT) == 0U);
1307
1308 if (!gicr_frame_found) {
1309 return -1;
1310 }
1311
1312 /*
1313 * Flush the driver data to ensure coherency. This is
1314 * not required if platform has HW_ASSISTED_COHERENCY
1315 * enabled.
1316 */
1317 #if !HW_ASSISTED_COHERENCY
1318 /*
1319 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
1320 */
1321 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]),
1322 sizeof(*(gicv3_driver_data->rdistif_base_addrs)));
1323 #endif
1324 return 0; /* Found matching GICR frame */
1325 }
1326
1327 /******************************************************************************
1328 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs
1329 * and false for (E)SPIs IDs.
1330 *****************************************************************************/
is_sgi_ppi(unsigned int id)1331 static bool is_sgi_ppi(unsigned int id)
1332 {
1333 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
1334 if (IS_SGI_PPI(id)) {
1335 return true;
1336 }
1337
1338 /* SPIs: 32-1019, ESPIs: 4096-5119 */
1339 if (IS_SPI(id)) {
1340 return false;
1341 }
1342
1343 assert(false);
1344 panic();
1345 }
1346
