1#
2# Tigerlake differentiation for pipelines and components
3#
4
5include(`memory.m4')
6
7dnl Memory capabilities for different buffer types on Tigerlake
8define(`PLATFORM_DAI_MEM_CAP',
9	MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
10define(`PLATFORM_HOST_MEM_CAP',
11	MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
12define(`PLATFORM_PASS_MEM_CAP',
13	MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
14define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE))
15
16# Low Latency PCM Configuration
17W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens,
18		LIST(`		', `SOF_TKN_SCHED_MIPS	"50000"'))
19
20W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens)
21
22# Media PCM Configuration
23W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens,
24		LIST(`		', `SOF_TKN_SCHED_MIPS	"100000"'))
25
26W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens)
27
28# Tone Signal Generator Configuration
29W_VENDORTUPLES(pipe_tone_schedule_plat_tokens, sof_sched_tokens,
30		LIST(`		', `SOF_TKN_SCHED_MIPS	"200000"'))
31
32W_DATA(pipe_tone_schedule_plat, pipe_tone_schedule_plat_tokens)
33
34# DAI schedule Configuration - scheduled by IRQ
35W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens,
36		LIST(`		', `SOF_TKN_SCHED_MIPS	"5000"'))
37
38W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens)
39