1 // SPDX-License-Identifier: BSD-3-Clause
2 //
3 //Copyright(c) 2022 AMD. All rights reserved.
4 //
5 //Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
6 // Bala Kishore <balakishore.pati@amd.com>
7
8 #include <sof/compiler_info.h>
9 #include <sof/debug/debug.h>
10 #include <rtos/interrupt.h>
11 #include <sof/drivers/acp_dai_dma.h>
12 #include <sof/ipc/driver.h>
13 #include <rtos/timer.h>
14 #include <sof/fw-ready-metadata.h>
15 #include <sof/lib/agent.h>
16 #include <rtos/clk.h>
17 #include <sof/lib/cpu.h>
18 #include <sof/lib/dai.h>
19 #include <sof/lib/dma.h>
20 #include <sof/lib/mailbox.h>
21 #include <sof/lib/memory.h>
22 #include <sof/lib/mm_heap.h>
23 #include <sof/platform.h>
24 #include <sof/schedule/edf_schedule.h>
25 #include <sof/schedule/ll_schedule.h>
26 #include <sof/schedule/ll_schedule_domain.h>
27 #include <rtos/sof.h>
28 #include <sof/trace/dma-trace.h>
29 #include <ipc/dai.h>
30 #include <ipc/header.h>
31 #include <ipc/info.h>
32 #include <kernel/abi.h>
33 #include <kernel/ext_manifest.h>
34 #include <sof_versions.h>
35 #include <errno.h>
36 #include <stdint.h>
37 #include <platform/chip_offset_byte.h>
38
39 struct sof;
40 static const struct sof_ipc_fw_ready ready
41 __attribute__((section(".fw_ready"))) = {
42 .hdr = {
43 .cmd = SOF_IPC_FW_READY,
44 .size = sizeof(struct sof_ipc_fw_ready),
45 },
46 /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
47 .version = {
48 .hdr.size = sizeof(struct sof_ipc_fw_version),
49 .micro = SOF_MICRO,
50 .minor = SOF_MINOR,
51 .major = SOF_MAJOR,
52 #ifdef DEBUG_BUILD
53 /* only added in debug for reproducability in releases */
54 .build = SOF_BUILD,
55 .date = __DATE__,
56 .time = __TIME__,
57 #endif
58 .tag = SOF_TAG,
59 .abi_version = SOF_ABI_VERSION,
60 },
61 .flags = DEBUG_SET_FW_READY_FLAGS,
62 };
63
64 #define NUM_ACP_WINDOWS 6
65
66 const struct ext_man_windows xsram_window
67 __aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = {
68 .hdr = {
69 .type = EXT_MAN_ELEM_WINDOW,
70 .elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN),
71 },
72 .window = {
73 .ext_hdr = {
74 .hdr.cmd = SOF_IPC_FW_READY,
75 .hdr.size = sizeof(struct sof_ipc_window),
76 .type = SOF_IPC_EXT_WINDOW,
77 },
78 .num_windows = NUM_ACP_WINDOWS,
79 .window = {
80 {
81 .type = SOF_IPC_REGION_UPBOX,
82 .id = 0,
83 .flags = 0,
84 .size = MAILBOX_DSPBOX_SIZE,
85 .offset = MAILBOX_DSPBOX_OFFSET,
86 },
87 {
88 .type = SOF_IPC_REGION_DOWNBOX,
89 .id = 0,
90 .flags = 0,
91 .size = MAILBOX_HOSTBOX_SIZE,
92 .offset = MAILBOX_HOSTBOX_OFFSET,
93 },
94 {
95 .type = SOF_IPC_REGION_DEBUG,
96 .id = 0,
97 .flags = 0,
98 .size = MAILBOX_DEBUG_SIZE,
99 .offset = MAILBOX_DEBUG_OFFSET,
100 },
101 {
102 .type = SOF_IPC_REGION_TRACE,
103 .id = 0,
104 .flags = 0,
105 .size = MAILBOX_TRACE_SIZE,
106 .offset = MAILBOX_TRACE_OFFSET,
107 },
108 {
109 .type = SOF_IPC_REGION_STREAM,
110 .id = 0,
111 .flags = 0,
112 .size = MAILBOX_STREAM_SIZE,
113 .offset = MAILBOX_STREAM_OFFSET,
114 },
115 {
116 .type = SOF_IPC_REGION_EXCEPTION,
117 .id = 0,
118 .flags = 0,
119 .size = MAILBOX_EXCEPTION_SIZE,
120 .offset = MAILBOX_EXCEPTION_OFFSET,
121 },
122 },
123 },
124 };
125
126 static SHARED_DATA struct timer timer = {
127 .id = TIMER0,
128 .irq = IRQ_NUM_TIMER0,
129 };
130
platform_init(struct sof * sof)131 int platform_init(struct sof *sof)
132 {
133 int ret;
134
135 sof->platform_timer = &timer;
136 sof->cpu_timers = &timer;
137 /* to view system memory */
138 platform_interrupt_init();
139 platform_clock_init(sof);
140 scheduler_init_edf();
141 /* init low latency domains and schedulers */
142 /* CONFIG_SYSTICK_PERIOD set as PLATFORM_DEFAULT_CLOCK */
143 sof->platform_timer_domain = timer_domain_init(sof->platform_timer,
144 PLATFORM_DEFAULT_CLOCK);
145 scheduler_init_ll(sof->platform_timer_domain);
146 platform_timer_start(sof->platform_timer);
147 /*CONFIG_SYSTICK_PERIOD hardcoded as 200000*/
148 sa_init(sof, 200000);
149 clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
150 /* init DMA */
151 ret = acp_dma_init(sof);
152 if (ret < 0)
153 return -ENODEV;
154 /* Init DMA platform domain */
155 sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0],
156 sizeof(sof->dma_info->dma_array), PLATFORM_DEFAULT_CLOCK, true);
157 sof->platform_dma_domain->full_sync = true;
158 scheduler_init_ll(sof->platform_dma_domain);
159 /* initialize the host IPC mechanisms */
160 ipc_init(sof);
161 /* initialize the DAI mechanisms */
162 ret = dai_init(sof);
163 if (ret < 0)
164 return -ENODEV;
165 #if CONFIG_TRACE
166 /* Initialize DMA for Trace*/
167 trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE);
168 sof->dmat->config.elem_array.elems = rzalloc(SOF_MEM_ZONE_RUNTIME, 0, SOF_MEM_CAPS_RAM,
169 sizeof(struct dma_sg_elem) * 1);
170 sof->dmat->config.elem_array.count = 1;
171 sof->dmat->config.elem_array.elems->dest = 0x03800000;
172 sof->dmat->config.elem_array.elems->size = 65536;
173 sof->dmat->config.scatter = 0;
174 dma_trace_init_complete(sof->dmat);
175 #endif
176 /* show heap status */
177 heap_trace_all(1);
178 return 0;
179 }
180
platform_boot_complete(uint32_t boot_message)181 int platform_boot_complete(uint32_t boot_message)
182 {
183 acp_sw_intr_trig_t swintrtrig;
184
185 volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
186 (volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
187 mailbox_dspbox_write(0, &ready, sizeof(ready));
188 pscratch_mem_cfg->acp_dsp_msg_write = 1;
189 acp_dsp_to_host_intr_trig();
190 /* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
191 swintrtrig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
192 swintrtrig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
193 io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), swintrtrig.u32all);
194 clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
195 return 0;
196 }
platform_context_save(struct sof * sof)197 int platform_context_save(struct sof *sof)
198 {
199 return 0;
200 }
201
platform_wait_for_interrupt(int level)202 void platform_wait_for_interrupt(int level)
203 {
204 arch_wait_for_interrupt(level);
205 }
206
