1#
2# Topology for Icelake with rt711 + rt1308 (x2) + rt715.
3#
4
5# Include topology builder
6include(`utils.m4')
7include(`dai.m4')
8include(`pipeline.m4')
9include(`alh.m4')
10include(`muxdemux.m4')
11include(`hda.m4')
12
13# Include TLV library
14include(`common/tlv.m4')
15
16# Include Token library
17include(`sof/tokens.m4')
18
19# Include Platform specific DSP configuration
20include(`platform/intel/'PLATFORM`.m4')
21
22ifdef(`UAJ_LINK',`',
23`define(UAJ_LINK, `0')')
24
25ifdef(`AMP_1_LINK',`',
26`define(AMP_1_LINK, `1')')
27
28ifdef(`AMP_2_LINK',`',
29`define(AMP_2_LINK, `2')')
30
31ifdef(`MIC_LINK',`',
32`define(MIC_LINK, `3')')
33
34DEBUG_START
35
36dnl Configure demux
37dnl name, pipeline_id, routing_matrix_rows
38dnl Diagonal 1's in routing matrix mean that every input channel is
39dnl copied to corresponding output channels in all output streams.
40dnl I.e. row index is the input channel, 1 means it is copied to
41dnl corresponding output channel (column index), 0 means it is discarded.
42dnl There's a separate matrix for all outputs.
43ifdef(`MONO', `',
44`
45define(matrix1, `ROUTE_MATRIX(3,
46			     `BITS_TO_BYTE(1, 0, 0 ,0 ,0 ,0 ,0 ,0)',
47			     `BITS_TO_BYTE(0, 1, 0 ,0 ,0 ,0 ,0 ,0)',
48			     `BITS_TO_BYTE(0, 0, 1 ,0 ,0 ,0 ,0 ,0)',
49			     `BITS_TO_BYTE(0, 0, 0 ,1 ,0 ,0 ,0 ,0)',
50			     `BITS_TO_BYTE(0, 0, 0 ,0 ,1 ,0 ,0 ,0)',
51			     `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,1 ,0 ,0)',
52			     `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,1 ,0)',
53			     `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,1)')')
54
55define(matrix2, `ROUTE_MATRIX(4,
56			     `BITS_TO_BYTE(1, 0, 0 ,0 ,0 ,0 ,0 ,0)',
57			     `BITS_TO_BYTE(0, 1, 0 ,0 ,0 ,0 ,0 ,0)',
58			     `BITS_TO_BYTE(0, 0, 1 ,0 ,0 ,0 ,0 ,0)',
59			     `BITS_TO_BYTE(0, 0, 0 ,1 ,0 ,0 ,0 ,0)',
60			     `BITS_TO_BYTE(0, 0, 0 ,0 ,1 ,0 ,0 ,0)',
61			     `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,1 ,0 ,0)',
62			     `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,1 ,0)',
63			     `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,1)')')
64
65dnl name, num_streams, route_matrix list
66MUXDEMUX_CONFIG(demux_priv_3, 2, LIST(`	', `matrix1,', `matrix2'))
67')
68
69#
70# Define the pipelines
71#
72ifdef(`NOJACK', `',
73`
74# PCM0 ---> volume ----> ALH 2 BE dailink 0
75# PCM1 <--- volume <---- ALH 3 BE dailink 1
76')
77# PCM2 ---> volume ----> ALH 2 BE dailink 2
78ifdef(`MONO', `',
79`# PCM40 ---> volume ----> ALH 2 BE dailink 3')
80# PCM4 <--- volume <---- ALH 2 BE dailink 4
81# PCM5 ---> volume ----> iDisp1
82# PCM6 ---> volume ----> iDisp2
83# PCM7 ---> volume ----> iDisp3
84
85dnl PIPELINE_PCM_ADD(pipeline,
86dnl     pipe id, pcm, max channels, format,
87dnl     period, priority, core,
88dnl     pcm_min_rate, pcm_max_rate, pipeline_rate,
89dnl     time_domain, sched_comp)
90
91ifdef(`NOJACK', `',
92`
93# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
94# Schedule 48 frames per 1000us deadline on core 0 with priority 0
95PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
96	1, 0, 2, s32le,
97	1000, 0, 0,
98	48000, 48000, 48000)
99
100# Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le.
101# Schedule 48 frames per 1000us deadline on core 0 with priority 0
102PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
103	2, 1, 2, s32le,
104	1000, 0, 0,
105	48000, 48000, 48000)
106')
107
108ifdef(`MONO',
109`
110# Low Latency playback pipeline 3 on PCM 2 using max 2 channels of s32le.
111# Schedule 48 frames per 1000us deadline on core 0 with priority 0
112PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
113	3, 2, 2, s32le,
114	1000, 0, 0,
115	48000, 48000, 48000)
116',
117`
118# Low Latency playback pipeline 3 on PCM 2 using max 2 channels of s32le.
119# Schedule 48 frames per 1000us deadline on core 0 with priority 0
120PIPELINE_PCM_ADD(ifdef(`NO_AGGREGATION',`sof/pipe-volume-playback.m4',
121	`sof/pipe-volume-demux-playback.m4'),
122	3, 2, 2, s32le,
123	1000, 0, 0,
124	48000, 48000, 48000)
125
126# Low Latency playback pipeline 4 on PCM 40 using max 2 channels of s32le.
127# Schedule 48 frames per 1000us deadline on core 0 with priority 0
128PIPELINE_PCM_ADD(ifdef(`NO_AGGREGATION', `sof/pipe-volume-playback.m4',
129	`sof/pipe-dai-endpoint.m4'),
130	4, 40, 2, s32le,
131	1000, 0, 0,
132	48000, 48000, 48000)
133')
134
135# Low Latency capture pipeline 5 on PCM 4 using max 2 channels of s32le.
136# Schedule 48 frames per 1000us deadline on core 0 with priority 0
137PIPELINE_PCM_ADD(sof/pipe-highpass-switch-capture.m4,
138	5, 4, 2, s32le,
139	1000, 0, 0,
140	48000, 48000, 48000)
141
142# Low Latency playback pipeline 6 on PCM 5 using max 2 channels of s32le.
143# Schedule 48 frames per 1000us deadline on core 0 with priority 0
144PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
145	6, 5, 2, s32le,
146	1000, 0, 0,
147	48000, 48000, 48000)
148
149# Low Latency playback pipeline 7 on PCM 6 using max 2 channels of s32le.
150# Schedule 48 frames per 1000us deadline on core 0 with priority 0
151PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
152	7, 6, 2, s32le,
153	1000, 0, 0,
154	48000, 48000, 48000)
155
156# Low Latency playback pipeline 8 on PCM 7 using max 2 channels of s32le.
157# Schedule 48 frames per 1000us deadline on core 0 with priority 0
158PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
159	8, 7, 2, s32le,
160	1000, 0, 0,
161	48000, 48000, 48000)
162
163#
164# DAIs configuration
165#
166
167dnl DAI_ADD(pipeline,
168dnl     pipe id, dai type, dai_index, dai_be,
169dnl     buffer, periods, format,
170dnl     deadline, priority, core, time_domain)
171
172ifdef(`NOJACK', `',
173`
174# playback DAI is ALH(SDW0 PIN2) using 2 periods
175# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
176DAI_ADD(sof/pipe-dai-playback.m4,
177	1, ALH, eval(UAJ_LINK * 256 + 2), `SDW'eval(UAJ_LINK)`-Playback',
178	PIPELINE_SOURCE_1, 2, s24le,
179	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
180
181# capture DAI is ALH(SDW0 PIN2) using 2 periods
182# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
183DAI_ADD(sof/pipe-dai-capture.m4,
184	2, ALH, eval(UAJ_LINK * 256 + 3), `SDW'eval(UAJ_LINK)`-Capture',
185	PIPELINE_SINK_2, 2, s24le,
186	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
187')
188
189# playback DAI is ALH(SDW1 PIN2) using 2 periods
190# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
191DAI_ADD(sof/pipe-dai-playback.m4,
192	3, ALH, eval(AMP_1_LINK * 256 + 2), `SDW'eval(AMP_1_LINK)`-Playback',
193	PIPELINE_SOURCE_3, 2, s24le,
194	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
195
196ifdef(`NO_AGGREGATION',
197`# playback DAI is ALH(SDW2 PIN2) using 2 periods
198# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
199DAI_ADD(sof/pipe-dai-playback.m4,
200	4, ALH, eval(AMP_2_LINK * 256 + 2), `SDW'eval(AMP_2_LINK)`-Playback',
201	PIPELINE_SOURCE_4, 2, s24le,
202	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)',
203`ifdef(`MONO', `',
204`DAI_ADD_SCHED(sof/pipe-dai-sched-playback.m4,
205	4, ALH, eval(AMP_2_LINK * 256 + 2), `SDW'eval(AMP_1_LINK)`-Playback',
206	PIPELINE_SOURCE_4, 2, s24le,
207	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER,
208	PIPELINE_PLAYBACK_SCHED_COMP_3)
209
210# Connect demux to 2nd pipeline
211SectionGraph."PIPE_DEMUX" {
212	index "4"
213
214	lines [
215		# mux to 2nd pipeline
216		dapm(PIPELINE_SOURCE_4, PIPELINE_DEMUX_3)
217	]
218}
219')')
220
221# capture DAI is ALH(SDW3 PIN2) using 2 periods
222# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
223DAI_ADD(sof/pipe-dai-capture.m4,
224	5, ALH, eval(MIC_LINK * 256 + 2), `SDW'eval(MIC_LINK)`-Capture',
225	PIPELINE_SINK_5, 2, s24le,
226	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
227
228# playback DAI is iDisp1 using 2 periods
229# # Buffers use s32le format, 1000us deadline on core 0 with priority 0
230DAI_ADD(sof/pipe-dai-playback.m4,
231	6, HDA, 0, iDisp1,
232	PIPELINE_SOURCE_6, 2, s32le,
233	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
234
235# playback DAI is iDisp2 using 2 periods
236# # Buffers use s32le format, 1000us deadline on core 0 with priority 0
237DAI_ADD(sof/pipe-dai-playback.m4,
238	7, HDA, 1, iDisp2,
239	PIPELINE_SOURCE_7, 2, s32le,
240	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
241
242# playback DAI is iDisp3 using 2 periods
243# # Buffers use s32le format, 1000us deadline on core 0 with priority 0
244DAI_ADD(sof/pipe-dai-playback.m4,
245	8, HDA, 2, iDisp3,
246	PIPELINE_SOURCE_8, 2, s32le,
247	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
248
249# PCM Low Latency, id 0
250dnl PCM_PLAYBACK_ADD(name, pcm_id, playback)
251
252ifdef(`NOJACK', `',
253`
254PCM_PLAYBACK_ADD(Jack Out, 0, PIPELINE_PCM_1)
255PCM_CAPTURE_ADD(Jack In, 1, PIPELINE_PCM_2)
256')
257
258PCM_PLAYBACK_ADD(Speaker, 2, PIPELINE_PCM_3)
259ifdef(`NO_AGGREGATION', `PCM_PLAYBACK_ADD(Speaker 2, 40, PIPELINE_PCM_4)',`')
260PCM_CAPTURE_ADD(Microphone, 4, PIPELINE_PCM_5)
261PCM_PLAYBACK_ADD(HDMI 1, 5, PIPELINE_PCM_6)
262PCM_PLAYBACK_ADD(HDMI 2, 6, PIPELINE_PCM_7)
263PCM_PLAYBACK_ADD(HDMI 3, 7, PIPELINE_PCM_8)
264
265#
266# BE configurations - overrides config in ACPI if present
267#
268
269ifdef(`NOJACK', `',
270`
271#ALH dai index = ((link_id << 8) | PDI id)
272#ALH SDW0 Pin2 (ID: 0)
273DAI_CONFIG(ALH, eval(UAJ_LINK * 256 + 2), 0, `SDW'eval(UAJ_LINK)`-Playback',
274	ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(UAJ_LINK * 256 + 2), 48000, 2)))
275
276#ALH SDW0 Pin3 (ID: 1)
277DAI_CONFIG(ALH, eval(UAJ_LINK * 256 + 3), 1, `SDW'eval(UAJ_LINK)`-Capture',
278	ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(UAJ_LINK * 256 + 3), 48000, 2)))
279')
280
281#ALH SDW1 Pin2 (ID: 2)
282DAI_CONFIG(ALH, eval(AMP_1_LINK * 256 + 2), 2, `SDW'eval(AMP_1_LINK)`-Playback',
283	ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(AMP_1_LINK * 256 + 2), 48000, 2)))
284
285ifdef(`NO_AGGREGATION',
286`#ALH SDW2 Pin2 (ID: 3)
287DAI_CONFIG(ALH, eval(AMP_2_LINK * 256 + 2), 3, `SDW'eval(AMP_2_LINK)`-Playback',
288	ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(AMP_2_LINK * 256 + 2), 48000, 2)))',
289`')
290
291#ALH SDW3 Pin2 (ID: 4)
292DAI_CONFIG(ALH, eval(MIC_LINK * 256 + 2), 4, `SDW'eval(MIC_LINK)`-Capture',
293	ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(MIC_LINK * 256 + 2), 48000, 2)))
294
295# 3 HDMI/DP outputs (ID: 5,6,7)
296DAI_CONFIG(HDA, 0, 5, iDisp1,
297	HDA_CONFIG(HDA_CONFIG_DATA(HDA, 0, 48000, 2)))
298DAI_CONFIG(HDA, 1, 6, iDisp2,
299	HDA_CONFIG(HDA_CONFIG_DATA(HDA, 1, 48000, 2)))
300DAI_CONFIG(HDA, 2, 7, iDisp3,
301	HDA_CONFIG(HDA_CONFIG_DATA(HDA, 2, 48000, 2)))
302
303DEBUG_END
304