1# 2# Topology for digital microphones array 3# 4 5include(`platform/intel/dmic.m4') 6 7# define default PCM names 8ifdef(`DMIC_48k_PCM_NAME',`', 9`define(DMIC_48k_PCM_NAME, `DMIC')') 10ifdef(`DMIC_16k_PCM_NAME',`', 11`define(DMIC_16k_PCM_NAME, `DMIC16kHz')') 12 13# variable that need to be defined in upper m4 14ifdef(`CHANNELS',`',`fatal_error(note: Need to define channel number for intel-generic-dmic 15)') 16ifdef(`DMIC_PCM_48k_ID',`',`fatal_error(note: Need to define dmic48k pcm id for intel-generic-dmic 17)') 18ifdef(`DMIC_PIPELINE_48k_ID',`',`fatal_error(note: Need to define dmic48k pipeline id for intel-generic-dmic 19)') 20ifdef(`DMIC_DAI_LINK_48k_ID',`',`fatal_error(note: Need to define dmic48k dai id for intel-generic-dmic 21)') 22 23ifdef(`DMIC_PCM_16k_ID',`',`fatal_error(note: Need to define dmic16k pcm id for intel-generic-dmic 24)') 25ifdef(`DMIC_PIPELINE_16k_ID',`',`fatal_error(note: Need to define dmic16k pipeline id for intel-generic-dmic 26)') 27ifdef(`DMIC_DAI_LINK_16k_ID',`',`fatal_error(note: Need to define dmic16k dai id for intel-generic-dmic 28)') 29 30# define(DMIC_DAI_LINK_48k_NAME, `dmic01') 31ifdef(`DMIC_DAI_LINK_48k_NAME',`',define(DMIC_DAI_LINK_48k_NAME, `dmic01')) 32 33# define(DMIC_DAI_LINK_16k_NAME, `dmic16k') 34ifdef(`DMIC_DAI_LINK_16k_NAME',`',define(DMIC_DAI_LINK_16k_NAME, `dmic16k')) 35 36ifdef(`DMIC_48k_CORE_ID',`', define(DMIC_48k_CORE_ID, `0')) 37ifdef(`DMIC_16k_CORE_ID',`', define(DMIC_16k_CORE_ID, `0')) 38 39# Handle possible different channels count for PCM and DAI 40ifdef(`DMIC_DAI_CHANNELS', `', `define(DMIC_DAI_CHANNELS, CHANNELS)') 41ifdef(`DMIC_PCM_CHANNELS', `', `define(DMIC_PCM_CHANNELS, CHANNELS)') 42ifdef(`DMIC16K_DAI_CHANNELS', `', `define(DMIC16K_DAI_CHANNELS, CHANNELS)') 43ifdef(`DMIC16K_PCM_CHANNELS', `', `define(DMIC16K_PCM_CHANNELS, CHANNELS)') 44 45## Prolong period to 4ms for RTNR 46ifdef(`RTNR', `define(`INTEL_GENERIC_DMIC_PERIOD', 4000)', `define(`INTEL_GENERIC_DMIC_PERIOD', 1000)') 47ifdef(`RTNR', `define(`INTEL_GENERIC_DMIC_PERIOD_INV', 250)', `define(`INTEL_GENERIC_DMIC_PERIOD_INV', 1000)') 48 49ifelse(CHANNELS, 1, `define(`VOLUME_CHANNEL_MAP', LIST(` ', KCONTROL_CHANNEL(FL, 1, 0)))') 50ifelse(CHANNELS, 2, `define(`VOLUME_CHANNEL_MAP', LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), 51 KCONTROL_CHANNEL(FR, 1, 1)))') 52ifelse(CHANNELS, 3, `define(`VOLUME_CHANNEL_MAP', LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), 53 KCONTROL_CHANNEL(FC, 1, 1), 54 KCONTROL_CHANNEL(FR, 1, 2)))') 55ifelse(CHANNELS, 4, `define(`VOLUME_CHANNEL_MAP', LIST(` ', KCONTROL_CHANNEL(FLW, 1, 0), 56 KCONTROL_CHANNEL(FL, 1, 1), 57 KCONTROL_CHANNEL(FR, 1, 2), 58 KCONTROL_CHANNEL(FRW, 1, 3)))') 59 60ifelse(CHANNELS, 1, `define(`SWITCH_CHANNEL_MAP', LIST(` ', KCONTROL_CHANNEL(FL, 2, 0)))') 61ifelse(CHANNELS, 2, `define(`SWITCH_CHANNEL_MAP', LIST(` ', KCONTROL_CHANNEL(FL, 2, 0), 62 KCONTROL_CHANNEL(FR, 2, 1)))') 63ifelse(CHANNELS, 3, `define(`SWITCH_CHANNEL_MAP', LIST(` ', KCONTROL_CHANNEL(FL, 2, 0), 64 KCONTROL_CHANNEL(FC, 2, 1), 65 KCONTROL_CHANNEL(FR, 2, 2)))') 66ifelse(CHANNELS, 4, `define(`SWITCH_CHANNEL_MAP', LIST(` ', KCONTROL_CHANNEL(FLW, 2, 0), 67 KCONTROL_CHANNEL(FL, 2, 1), 68 KCONTROL_CHANNEL(FR, 2, 2), 69 KCONTROL_CHANNEL(FRW, 2, 3)))') 70# 71# Define the pipelines 72# 73 74dnl PIPELINE_PCM_ADD(pipeline, 75dnl pipe id, pcm, max channels, format, 76dnl period, priority, core, 77dnl pcm_min_rate, pcm_max_rate, pipeline_rate, 78dnl time_domain, sched_comp) 79 80# Passthrough capture pipeline using max channels defined by DMIC_PCM_CHANNELS. 81 82# Set 1000us deadline on core 0 with priority 0 83ifdef(`DMICPROC_FILTER1', `define(PIPELINE_FILTER1, DMICPROC_FILTER1)', `undefine(`PIPELINE_FILTER1')') 84ifdef(`DMICPROC_FILTER2', `define(PIPELINE_FILTER2, DMICPROC_FILTER2)', `undefine(`PIPELINE_FILTER2')') 85define(`PGA_NAME', Dmic0) 86 87PIPELINE_PCM_ADD(sof/pipe-DMICPROC-capture.m4, 88 DMIC_PIPELINE_48k_ID, DMIC_PCM_48k_ID, DMIC_PCM_CHANNELS, s32le, 89 1000, 0, DMIC_48k_CORE_ID, 48000, 48000, 48000) 90 91undefine(`PGA_NAME') 92undefine(`PIPELINE_FILTER1') 93undefine(`PIPELINE_FILTER2') 94 95# Passthrough capture pipeline using max channels defined by CHANNELS. 96 97# Schedule with 1000us deadline on core 0 with priority 0 98ifdef(`DMIC16KPROC_FILTER1', `define(PIPELINE_FILTER1, DMIC16KPROC_FILTER1)', `undefine(`PIPELINE_FILTER1')') 99ifdef(`DMIC16KPROC_FILTER2', `define(PIPELINE_FILTER2, DMIC16KPROC_FILTER2)', `undefine(`PIPELINE_FILTER2')') 100define(`PGA_NAME', Dmic1) 101 102PIPELINE_PCM_ADD(sof/pipe-DMIC16KPROC-capture-16khz.m4, 103 DMIC_PIPELINE_16k_ID, DMIC_PCM_16k_ID, DMIC16K_PCM_CHANNELS, s32le, 104 INTEL_GENERIC_DMIC_PERIOD_INV, 0, DMIC_16k_CORE_ID, 16000, 16000, 16000) 105 106undefine(`PGA_NAME') 107undefine(`PIPELINE_FILTER1') 108undefine(`PIPELINE_FILTER2') 109undefine(`VOLUME_CHANNEL_MAP') 110undefine(`SWITCH_CHANNEL_MAP') 111 112# 113# DAIs configuration 114# 115 116dnl DAI_ADD(pipeline, 117dnl pipe id, dai type, dai_index, dai_be, 118dnl buffer, periods, format, 119dnl deadline, priority, core, time_domain) 120 121# capture DAI is DMIC 0 using 2 periods 122# Buffers use s32le format, 1000us deadline on core 0 with priority 0 123DAI_ADD(sof/pipe-dai-capture.m4, 124 DMIC_PIPELINE_48k_ID, DMIC, 0, DMIC_DAI_LINK_48k_NAME, 125 concat(`PIPELINE_SINK_', DMIC_PIPELINE_48k_ID), 2, s32le, 126 1000, 0, DMIC_48k_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER) 127 128# capture DAI is DMIC 1 using 2 periods 129# Buffers use s32le format, with 16 frame per 1000us on core 0 with priority 0 130DAI_ADD(sof/pipe-dai-capture.m4, 131 DMIC_PIPELINE_16k_ID, DMIC, 1, DMIC_DAI_LINK_16k_NAME, 132 concat(`PIPELINE_SINK_', DMIC_PIPELINE_16k_ID), 2, s32le, 133 INTEL_GENERIC_DMIC_PERIOD, 0, DMIC_16k_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER) 134 135dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) 136dnl PCM_CAPTURE_ADD(name, pipeline, capture) 137PCM_CAPTURE_ADD(DMIC_48k_PCM_NAME, DMIC_PCM_48k_ID, concat(`PIPELINE_PCM_', DMIC_PIPELINE_48k_ID)) 138PCM_CAPTURE_ADD(DMIC_16k_PCM_NAME, DMIC_PCM_16k_ID, concat(`PIPELINE_PCM_', DMIC_PIPELINE_16k_ID)) 139 140# 141# BE configurations - overrides config in ACPI if present 142# 143 144dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) 145ifelse(DMIC_DAI_CHANNELS, 4, 146`DAI_CONFIG(DMIC, 0, DMIC_DAI_LINK_48k_ID, DMIC_DAI_LINK_48k_NAME, 147 DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, 148 DMIC_WORD_LENGTH(s32le), 200, DMIC, 0, 149 PDM_CONFIG(DMIC, 0, FOUR_CH_PDM0_PDM1)))', 150`DAI_CONFIG(DMIC, 0, DMIC_DAI_LINK_48k_ID, DMIC_DAI_LINK_48k_NAME, 151 DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, 152 DMIC_WORD_LENGTH(s32le), 200, DMIC, 0, 153 PDM_CONFIG(DMIC, 0, STEREO_PDM0)))') 154 155ifelse(DMIC16K_DAI_CHANNELS, 4, 156`DAI_CONFIG(DMIC, 1, DMIC_DAI_LINK_16k_ID, DMIC_DAI_LINK_16k_NAME, 157 DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 16000, 158 DMIC_WORD_LENGTH(s32le), 400, DMIC, 1, 159 PDM_CONFIG(DMIC, 1, FOUR_CH_PDM0_PDM1)))', 160`DAI_CONFIG(DMIC, 1, DMIC_DAI_LINK_16k_ID, DMIC_DAI_LINK_16k_NAME, 161 DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 16000, 162 DMIC_WORD_LENGTH(s32le), 400, DMIC, 1, 163 PDM_CONFIG(DMIC, 1, STEREO_PDM0)))') 164
