1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2017 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 * Rander Wang <rander.wang@intel.com> 8 */ 9 10 #ifdef __SOF_LIB_SHIM_H__ 11 12 #ifndef __PLATFORM_LIB_SHIM_H__ 13 #define __PLATFORM_LIB_SHIM_H__ 14 15 #include <cavs/drivers/sideband-ipc.h> 16 #include <cavs/lib/shim.h> 17 #include <sof/bit.h> 18 #include <sof/lib/memory.h> 19 20 /* DSP IPC for Host Registers */ 21 #define IPC_DIPCTDR 0x00 22 #define IPC_DIPCTDA 0x04 23 #define IPC_DIPCTDD 0x08 24 #define IPC_DIPCIDR 0x10 25 #define IPC_DIPCIDA 0x14 26 #define IPC_DIPCIDD 0x18 27 #define IPC_DIPCCTL 0x28 28 29 #define IPC_DSP_OFFSET 0x10 30 31 /* DSP IPC for intra DSP communication */ 32 #define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) 33 #define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) 34 #define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) 35 #define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) 36 #define IPC_IDCCTL 0x50 37 38 /* IDCTFC */ 39 #define IPC_IDCTFC_BUSY (1 << 31) 40 #define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF 41 42 /* IDCTEFC */ 43 #define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF 44 45 /* IDCITC */ 46 #define IPC_IDCITC_BUSY (1 << 31) 47 #define IPC_IDCITC_MSG_MASK 0x7FFFFFFF 48 49 /* IDCIETC */ 50 #define IPC_IDCIETC_DONE (1 << 30) 51 #define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF 52 53 /* IDCCTL */ 54 #define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) 55 #define IPC_IDCCTL_IDCTBIE(x) (0x1 << (x)) 56 57 #define IRQ_CPU_OFFSET 0x40 58 59 #define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) 60 #define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) 61 #define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) 62 #define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) 63 64 /* all mask valid bits */ 65 #define REG_IRQ_IL2MD_ALL 0x03F181F0 66 67 #define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) 68 #define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) 69 #define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) 70 #define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) 71 72 /* all mask valid bits */ 73 #define REG_IRQ_IL3MD_ALL 0x807F81FF 74 75 #define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) 76 #define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) 77 #define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) 78 #define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) 79 80 /* all mask valid bits */ 81 #define REG_IRQ_IL4MD_ALL 0x807F81FF 82 83 #define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) 84 #define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) 85 #define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) 86 #define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) 87 88 /* all mask valid bits */ 89 #define REG_IRQ_IL5MD_ALL 0xFFFFC0CF 90 91 #define REG_IRQ_IL2RSD 0x100 92 #define REG_IRQ_IL3RSD 0x104 93 #define REG_IRQ_IL4RSD 0x108 94 #define REG_IRQ_IL5RSD 0x10c 95 96 #define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) 97 #define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) 98 99 /* DSP Shim Registers */ 100 #define SHIM_DSPWC 0x20 /* DSP Wall Clock */ 101 #define SHIM_DSPWCL 0x20 /* DSP Wall Clock Low */ 102 #define SHIM_DSPWCH 0x24 /* DSP Wall Clock High */ 103 #define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ 104 #define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ 105 #define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ 106 107 #define SHIM_DSPWCTCS_T1T (0x1 << 5) /* Timer 1 triggered */ 108 #define SHIM_DSPWCTCS_T0T (0x1 << 4) /* Timer 0 triggered */ 109 #define SHIM_DSPWCTCS_T1A (0x1 << 1) /* Timer 1 armed */ 110 #define SHIM_DSPWCTCS_T0A (0x1 << 0) /* Timer 0 armed */ 111 112 /** \brief Clock control */ 113 #define SHIM_CLKCTL 0x78 114 115 /** \brief Request HP RING Oscillator Clock */ 116 #define SHIM_CLKCTL_RHROSCC BIT(31) 117 118 /** \brief Request XTAL Oscillator Clock */ 119 #define SHIM_CLKCTL_RXOSCC BIT(30) 120 121 /** \brief Request LP RING Oscillator Clock */ 122 #define SHIM_CLKCTL_RLROSCC BIT(29) 123 124 /** \brief Oscillator Clock Select*/ 125 #define SHIM_CLKCTL_OCS_HP_RING BIT(2) 126 #define SHIM_CLKCTL_OCS_LP_RING 0 127 128 /** \brief LP Memory Clock Select */ 129 #define SHIM_CLKCTL_LMCS_DIV2 0 130 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) 131 132 /** \brief HP Memory Clock Select */ 133 #define SHIM_CLKCTL_HMCS_DIV2 0 134 #define SHIM_CLKCTL_HMCS_DIV4 BIT(0) 135 136 /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */ 137 #define SHIM_CLKCTL_TCPLCG(x) (0x1 << (16 + x)) 138 139 /* Core clock PLL divisor */ 140 #define SHIM_CLKCTL_DPCS_MASK(x) (0x1 << 2) 141 142 /* Prevent Audio PLL Shutdown */ 143 #define SHIM_CLKCTL_TCPAPLLS (0x1 << 7) 144 145 /* 0--from PLL, 1--from oscillator */ 146 #define SHIM_CLKCTL_HDCS (0x1 << 4) 147 148 /* Oscillator select */ 149 #define SHIM_CLKCTL_HDOCS (0x1 << 2) 150 151 /* HP memory clock PLL divisor */ 152 #define SHIM_CLKCTL_HPMPCS (0x1 << 0) 153 154 /** \brief Mask for requesting clock 155 */ 156 #define SHIM_CLKCTL_OSC_REQUEST_MASK \ 157 (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \ 158 SHIM_CLKCTL_RLROSCC) 159 160 /** \brief Mask for setting previously requested clock 161 */ 162 #define SHIM_CLKCTL_OSC_SOURCE_MASK \ 163 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \ 164 SHIM_CLKCTL_HMCS_DIV4) 165 166 /** \brief Clock status */ 167 #define SHIM_CLKSTS 0x7C 168 169 /** \brief HP RING Oscillator Clock Status */ 170 #define SHIM_CLKSTS_HROSCCS BIT(31) 171 172 /** \brief XTAL Oscillator Clock Status */ 173 #define SHIM_CLKSTS_XOSCCS BIT(30) 174 175 /** \brief LP RING Oscillator Clock Status */ 176 #define SHIM_CLKSTS_LROSCCS BIT(29) 177 178 #define SHIM_PWRCTL 0x90 179 #define SHIM_PWRCTL_TCPDSPPG(x) BIT(x) 180 #define SHIM_PWRCTL_TCPCTLPG BIT(4) 181 182 #define SHIM_PWRSTS 0x92 183 184 #define SHIM_LPSCTL 0x94 185 #define SHIM_LPSCTL_BID BIT(7) 186 #define SHIM_LPSCTL_FDSPRUN BIT(9) 187 #define SHIM_LPSCTL_BATTR_0 BIT(12) 188 189 /** \brief GPDMA shim registers Control */ 190 #define SHIM_GPDMA_BASE_OFFSET 0x6500 191 #define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100) 192 193 /** \brief GPDMA Clock Control */ 194 #define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4) 195 /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */ 196 #define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0) 197 198 /** \brief GPDMA Channel Linear Link Position Control */ 199 #define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10) 200 #define SHIM_GPDMA_CHLLPC_EN BIT(7) 201 #define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) 202 203 #define L2LMCAP 0x71D00 204 #define L2MPAT 0x71D04 205 206 #define HSPGCTL0 0x71D10 207 #define HSRMCTL0 0x71D14 208 #define HSPGISTS0 0x71D18 209 210 #define HSPGCTL1 0x71D20 211 #define HSRMCTL1 0x71D24 212 #define HSPGISTS1 0x71D28 213 214 #define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x)) 215 #define SHIM_HSRMCTL(x) (HSRMCTL0 + 0x10 * (x)) 216 #define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x)) 217 218 #define LSPGCTL 0x71D50 219 #define LSRMCTL 0x71D54 220 #define LSPGISTS 0x71D58 221 222 #define SHIM_L2_MECS (SHIM_BASE + 0xd0) 223 224 /** \brief LDO Control */ 225 #define SHIM_LDOCTL 0xA4 226 #define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) 227 #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) 228 #define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) 229 #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) 230 #define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (1 << 0) 231 #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS (1 << 2) 232 #define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) 233 #define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) 234 235 #define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) 236 #define LPGPDMA_CTLOSEL_FLAG (1 << 15) 237 #define LPGPDMA_CHOSEL_FLAG (0xFF) 238 239 #define DSP_INIT_IOPO 0x71A68 240 #define IOPO_DMIC_FLAG (1 << 0) 241 #define IOPO_I2S_FLAG (7 << 8) 242 243 #define DSP_INIT_GENO 0x71A6C 244 #define GENO_MDIVOSEL (1 << 1) 245 #define GENO_DIOPTOSEL (1 << 2) 246 247 #define DSP_INIT_ALHO 0x71A70 248 #define ALHO_ASO_FLAG (1 << 0) 249 #define ALHO_CSO_FLAG (1 << 1) 250 #define ALHO_CFO_FLAG (1 << 2) 251 252 #define SHIM_SVCFG 0xF4 253 #define SHIM_SVCFG_FORCE_L1_EXIT (0x1 << 1) 254 255 /* host windows */ 256 #define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) 257 #define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) 258 259 #define DMWBA_ENABLE (1 << 0) 260 #define DMWBA_READONLY (1 << 1) 261 262 /* DMIC power ON bit */ 263 #define DMICLCTL_SPA ((uint32_t) BIT(0)) 264 265 /* DMIC disable clock gating */ 266 #define DMIC_DCGD ((uint32_t) BIT(30)) 267 268 #endif /* __PLATFORM_LIB_SHIM_H__ */ 269 270 #else 271 272 #error "This file shouldn't be included from outside of sof/lib/shim.h" 273 274 #endif /* __SOF_LIB_SHIM_H__ */ 275
