1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ 6 7 /* Customer ID=4313; Build=0x5483b; Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #ifndef XTENSA_SPECREG_H 29 #define XTENSA_SPECREG_H 30 31 /* Include these special register bitfield definitions, for historical reasons: */ 32 #include <xtensa/corebits.h> 33 34 35 /* Special registers: */ 36 #define LBEG 0 37 #define LEND 1 38 #define LCOUNT 2 39 #define SAR 3 40 #define BR 4 41 #define SCOMPARE1 12 42 #define WINDOWBASE 72 43 #define WINDOWSTART 73 44 #define IBREAKENABLE 96 45 #define ATOMCTL 99 46 #define DDR 104 47 #define IBREAKA_0 128 48 #define IBREAKA_1 129 49 #define DBREAKA_0 144 50 #define DBREAKA_1 145 51 #define DBREAKC_0 160 52 #define DBREAKC_1 161 53 #define EPC_1 177 54 #define EPC_2 178 55 #define EPC_3 179 56 #define EPC_4 180 57 #define EPC_5 181 58 #define EPC_6 182 59 #define EPC_7 183 60 #define DEPC 192 61 #define EPS_2 194 62 #define EPS_3 195 63 #define EPS_4 196 64 #define EPS_5 197 65 #define EPS_6 198 66 #define EPS_7 199 67 #define EXCSAVE_1 209 68 #define EXCSAVE_2 210 69 #define EXCSAVE_3 211 70 #define EXCSAVE_4 212 71 #define EXCSAVE_5 213 72 #define EXCSAVE_6 214 73 #define EXCSAVE_7 215 74 #define CPENABLE 224 75 #define INTERRUPT 226 76 #define INTENABLE 228 77 #define PS 230 78 #define VECBASE 231 79 #define EXCCAUSE 232 80 #define DEBUGCAUSE 233 81 #define CCOUNT 234 82 #define PRID 235 83 #define ICOUNT 236 84 #define ICOUNTLEVEL 237 85 #define EXCVADDR 238 86 #define CCOMPARE_0 240 87 #define CCOMPARE_1 241 88 #define CCOMPARE_2 242 89 #define MISC_REG_0 244 90 #define MISC_REG_1 245 91 92 /* Special cases (bases of special register series): */ 93 #define IBREAKA 128 94 #define DBREAKA 144 95 #define DBREAKC 160 96 #define EPC 176 97 #define EPS 192 98 #define EXCSAVE 208 99 #define CCOMPARE 240 100 101 /* Special names for read-only and write-only interrupt registers: */ 102 #define INTREAD 226 103 #define INTSET 226 104 #define INTCLEAR 227 105 106 #endif /* XTENSA_SPECREG_H */ 107 108
