1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2017 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 * Rander Wang <rander.wang@intel.com> 8 */ 9 10 #ifdef __SOF_LIB_MEMORY_H__ 11 12 #ifndef __PLATFORM_LIB_MEMORY_H__ 13 #define __PLATFORM_LIB_MEMORY_H__ 14 15 #include <cavs/lib/memory.h> 16 #include <sof/lib/cpu.h> 17 18 /* physical DSP addresses */ 19 20 /* shim */ 21 #define SHIM_BASE 0x00071F00 22 #define SHIM_SIZE 0x00000100 23 24 /* Digital Mic Shim Registers */ 25 #define DMIC_SHIM_BASE 0x00071E80 26 #define DMICLCTL_OFFSET 0x04 27 #define DMICLCTL (DMIC_SHIM_BASE + DMICLCTL_OFFSET) 28 29 /* cmd IO to audio codecs */ 30 #define CMD_BASE 0x00001100 31 #define CMD_SIZE 0x00000010 32 33 /* resource allocation */ 34 #define RES_BASE 0x00001110 35 #define RES_SIZE 0x00000010 36 37 /* IPC to the host */ 38 #define IPC_HOST_BASE 0x00071E00 39 #define IPC_HOST_SIZE 0x00000020 40 41 /* intra DSP IPC */ 42 #define IPC_DSP_SIZE 0x00000080 43 #define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE) 44 45 /* SRAM window for HOST */ 46 #define HOST_WIN_SIZE 0x00000008 47 #define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE) 48 49 /* IRQ controller */ 50 #define IRQ_BASE 0x00078800 51 #define IRQ_SIZE 0x00000200 52 53 /* time stamping */ 54 #define TIME_BASE 0x00071800 55 #define TIME_SIZE 0x00000200 56 57 /* M/N dividers */ 58 #define MN_BASE 0x00078C00 59 #define MN_SIZE 0x00000200 60 61 /* low power DMA position */ 62 #define LP_GP_DMA_LINK_SIZE 0x00000010 63 #define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE) 64 65 /* high performance DMA position */ 66 #define HP_GP_DMA_LINK_SIZE 0x00000010 67 #define HP_GP_DMA_LINK_BASE(x) (0x00001D00 + x * HP_GP_DMA_LINK_SIZE) 68 69 /* link DMAC stream */ 70 #define GTW_LINK_OUT_STREAM_SIZE 0x00000020 71 #define GTW_LINK_OUT_STREAM_BASE(x) \ 72 (0x00072400 + x * GTW_LINK_OUT_STREAM_SIZE) 73 74 #define GTW_LINK_IN_STREAM_SIZE 0x00000020 75 #define GTW_LINK_IN_STREAM_BASE(x) \ 76 (0x00072600 + x * GTW_LINK_IN_STREAM_SIZE) 77 78 /* host DMAC stream */ 79 #define GTW_HOST_OUT_STREAM_SIZE 0x00000040 80 #define GTW_HOST_OUT_STREAM_BASE(x) \ 81 (0x00072800 + x * GTW_HOST_OUT_STREAM_SIZE) 82 83 #define GTW_HOST_IN_STREAM_SIZE 0x00000040 84 #define GTW_HOST_IN_STREAM_BASE(x) \ 85 (0x00072C00 + x * GTW_HOST_IN_STREAM_SIZE) 86 87 /* code loader */ 88 #define GTW_CODE_LDR_SIZE 0x00000040 89 #define GTW_CODE_LDR_BASE 0x00002BC0 90 91 /* L2 TLBs */ 92 #define L2_HP_SRAM_TLB_SIZE 0x00001000 93 #define L2_HP_SRAM_TLB_BASE 0x00003000 94 95 /* DMICs */ 96 #define DMIC_BASE 0x00010000 97 #define DMIC_SIZE 0x00008000 98 99 /* SSP */ 100 #define SSP_BASE(x) (0x00077000 + x * SSP_SIZE) 101 #define SSP_SIZE 0x0000200 102 103 /* ALH */ 104 #define ALH_BASE 0x000071000 105 #define ALH_TXDA_OFFSET 0x000000400 106 #define ALH_RXDA_OFFSET 0x000000500 107 #define ALH_STREAM_OFFSET 0x000000004 108 109 /* Timestamping */ 110 #define TIMESTAMP_BASE 0x00071800 111 112 /* low power DMACs */ 113 #define LP_GP_DMA_SIZE 0x00001000 114 #define LP_GP_DMA_BASE(x) (0x0007C000 + x * LP_GP_DMA_SIZE) 115 116 /* high performance DMACs */ 117 #define HP_GP_DMA_SIZE 0x00001000 118 #define HP_GP_DMA_BASE(x) (0x0000E000 + x * HP_GP_DMA_SIZE) 119 120 /* ROM */ 121 #define ROM_BASE 0xBEFE0000 122 #define ROM_SIZE 0x00002000 123 124 #define L2_VECTOR_SIZE 0x1000 125 126 #define UUID_ENTRY_ELF_BASE 0x1FFFA000 127 #define UUID_ENTRY_ELF_SIZE 0x6000 128 129 #define LOG_ENTRY_ELF_BASE 0x20000000 130 #define LOG_ENTRY_ELF_SIZE 0x2000000 131 132 #define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) 133 #define EXT_MANIFEST_ELF_SIZE 0x2000000 134 135 /* 136 * The HP SRAM Region on Cannonlake is organised like this :- 137 * +--------------------------------------------------------------------------+ 138 * | Offset | Region | Size | 139 * +------------------+-------------------------+-----------------------------+ 140 * | SRAM_SW_REG_BASE | SW Registers W0 | SRAM_SW_REG_SIZE | 141 * +------------------+-------------------------+-----------------------------+ 142 * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE | 143 * +------------------+-------------------------+-----------------------------+ 144 * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | 145 * +------------------+-------------------------+-----------------------------+ 146 * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | 147 * +------------------+-------------------------+-----------------------------+ 148 * | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE | 149 * +------------------+-------------------------+-----------------------------+ 150 * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE | 151 * +------------------+-------------------------+-----------------------------+ 152 * | SRAM_TRACE_BASE | Trace Buffer W3 | SRAM_TRACE_SIZE | 153 * +------------------+-------------------------+-----------------------------+ 154 * | SOF_FW_START | text | | 155 * | | data | | 156 * | | ----------------------- | | 157 * | ||BSS: || | 158 * | ||-----------------------++-----------------------------+ 159 * | ||Runtime Heap || HEAP_RUNTIME_SIZE | 160 * | ||-----------------------++-----------------------------+ 161 * | ||Runtime shared Heap || HEAP_RUNTIME_SHARED_SIZE | 162 * | ||-----------------------++-----------------------------+ 163 * | ||System shared Heap || HEAP_SYSTEM_SHARED_SIZE | 164 * | ||-----------------------++-----------------------------+ 165 * | ||Module Buffers || HEAP_BUFFER_SIZE | 166 * | ||-----------------------++-----------------------------+ 167 * | ||Primary core Sys Heap || HEAP_SYSTEM_M_SIZE | 168 * | ||-----------------------++-----------------------------+ 169 * | ||Pri. Sys Runtime Heap || HEAP_SYS_RUNTIME_M_SIZE | 170 * | ||-----------------------++-----------------------------+ 171 * | ||Primary core Stack || SOF_STACK_SIZE | 172 * | ||-----------------------++-----------------------------+ 173 * | ||Sec. core Sys Heap || SOF_CORE_S_T_SIZE | 174 * | ||Sec. Sys Runtime Heap || | 175 * | ||Secondary core Stack || | 176 * | | ----------------------- | | 177 * +------------------+-------------------------+-----------------------------+ 178 */ 179 180 /* HP SRAM */ 181 #define HP_SRAM_BASE 0xBE000000 182 183 /* HP SRAM windows */ 184 /* window 0 */ 185 #define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) 186 #define SRAM_SW_REG_SIZE 0x1000 187 188 #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) 189 #define SRAM_OUTBOX_SIZE 0x1000 190 191 /* window 1 */ 192 #define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) 193 #define SRAM_INBOX_SIZE 0x2000 194 195 /* window 2 */ 196 #define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) 197 #define SRAM_DEBUG_SIZE 0x800 198 199 #define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) 200 #define SRAM_EXCEPT_SIZE 0x800 201 202 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) 203 #define SRAM_STREAM_SIZE 0x1000 204 205 /* window 3 */ 206 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) 207 #if CONFIG_TRACE 208 #define SRAM_TRACE_SIZE 0x2000 209 #else 210 #define SRAM_TRACE_SIZE 0x0 211 #endif 212 213 #define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE 214 #define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) 215 #define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE 216 #define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE 217 #define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE 218 #define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \ 219 SRAM_STREAM_SIZE) 220 #define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE 221 #define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE 222 223 /* HP SRAM Base */ 224 #define HP_SRAM_VECBASE_RESET (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) 225 226 /* text and data share the same HP L2 SRAM on Cannonlake */ 227 #define SOF_FW_START (HP_SRAM_VECBASE_RESET + 0x400) 228 #define SOF_FW_BASE (SOF_FW_START) 229 230 /* max size for all var-size sections (text/rodata/bss) */ 231 #define SOF_FW_MAX_SIZE (HP_SRAM_BASE + HP_SRAM_SIZE - SOF_FW_BASE) 232 233 #define SOF_TEXT_START (SOF_FW_START) 234 #define SOF_TEXT_BASE (SOF_FW_START) 235 236 /* Heap section sizes for system runtime heap for primary core */ 237 #define HEAP_SYS_RT_0_COUNT64 128 238 #define HEAP_SYS_RT_0_COUNT512 16 239 #define HEAP_SYS_RT_0_COUNT1024 4 240 241 /* Heap section sizes for system runtime heap for secondary core */ 242 #define HEAP_SYS_RT_X_COUNT64 64 243 #define HEAP_SYS_RT_X_COUNT512 8 244 #define HEAP_SYS_RT_X_COUNT1024 4 245 246 /* Heap section counts base */ 247 #define HEAP_COUNT64 128 248 #define HEAP_COUNT128 128 249 #define HEAP_COUNT256 96 250 #define HEAP_COUNT512 8 251 #define HEAP_COUNT1024 4 252 #define HEAP_COUNT2048 2 253 #define HEAP_COUNT4096 1 254 255 #if HP_SRAM_SIZE < 0x200000 256 #define RT_TIMES 3 257 #define RT_SHARED_TIMES 6 258 #else 259 #define RT_TIMES 8 260 #define RT_SHARED_TIMES 16 261 #endif 262 263 /* Heap section sizes for module pool */ 264 #define HEAP_RT_COUNT64 (HEAP_COUNT64 * RT_TIMES) 265 #define HEAP_RT_COUNT128 (HEAP_COUNT128 * RT_TIMES) 266 #define HEAP_RT_COUNT256 (HEAP_COUNT256 * RT_TIMES) 267 #define HEAP_RT_COUNT512 (HEAP_COUNT512 * RT_TIMES) 268 #define HEAP_RT_COUNT1024 (HEAP_COUNT1024 * RT_TIMES) 269 #define HEAP_RT_COUNT2048 (HEAP_COUNT2048 * RT_TIMES) 270 #define HEAP_RT_COUNT4096 (HEAP_COUNT4096 * RT_TIMES) 271 272 /* Heap configuration */ 273 #define HEAP_RUNTIME_SIZE \ 274 (HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \ 275 HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \ 276 HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + \ 277 HEAP_RT_COUNT4096 * 4096) 278 279 /* Heap section sizes for runtime shared heap */ 280 #define HEAP_RUNTIME_SHARED_COUNT64 (HEAP_COUNT64 * RT_SHARED_TIMES) 281 #define HEAP_RUNTIME_SHARED_COUNT128 (HEAP_COUNT128 * RT_SHARED_TIMES) 282 #define HEAP_RUNTIME_SHARED_COUNT256 (HEAP_COUNT256 * RT_SHARED_TIMES) 283 #define HEAP_RUNTIME_SHARED_COUNT512 (HEAP_COUNT512 * RT_SHARED_TIMES) 284 #define HEAP_RUNTIME_SHARED_COUNT1024 (HEAP_COUNT1024 * RT_SHARED_TIMES) 285 286 #define HEAP_RUNTIME_SHARED_SIZE \ 287 (HEAP_RUNTIME_SHARED_COUNT64 * 64 + HEAP_RUNTIME_SHARED_COUNT128 * 128 + \ 288 HEAP_RUNTIME_SHARED_COUNT256 * 256 + HEAP_RUNTIME_SHARED_COUNT512 * 512 + \ 289 HEAP_RUNTIME_SHARED_COUNT1024 * 1024) 290 291 /* Heap section sizes for system shared heap */ 292 #define HEAP_SYSTEM_SHARED_SIZE 0x1500 293 294 #define HEAP_BUFFER_SIZE 0x50000 295 #define HEAP_BUFFER_BLOCK_SIZE 0x100 296 #define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) 297 298 #define HEAP_SYSTEM_M_SIZE 0x8000 /* heap primary core size */ 299 #define HEAP_SYSTEM_S_SIZE 0x6000 /* heap secondary core size */ 300 301 #define HEAP_SYSTEM_T_SIZE \ 302 (HEAP_SYSTEM_M_SIZE + ((CONFIG_CORE_COUNT - 1) * HEAP_SYSTEM_S_SIZE)) 303 304 #define HEAP_SYS_RUNTIME_M_SIZE \ 305 (HEAP_SYS_RT_0_COUNT64 * 64 + HEAP_SYS_RT_0_COUNT512 * 512 + \ 306 HEAP_SYS_RT_0_COUNT1024 * 1024) 307 308 #define HEAP_SYS_RUNTIME_S_SIZE \ 309 (HEAP_SYS_RT_X_COUNT64 * 64 + HEAP_SYS_RT_X_COUNT512 * 512 + \ 310 HEAP_SYS_RT_X_COUNT1024 * 1024) 311 312 #define HEAP_SYS_RUNTIME_T_SIZE \ 313 (HEAP_SYS_RUNTIME_M_SIZE + ((CONFIG_CORE_COUNT - 1) * \ 314 HEAP_SYS_RUNTIME_S_SIZE)) 315 316 /* Stack configuration */ 317 #define SOF_STACK_SIZE 0x1000 318 #define SOF_STACK_TOTAL_SIZE (CONFIG_CORE_COUNT * SOF_STACK_SIZE) 319 320 /* SOF Core S configuration */ 321 #define SOF_CORE_S_SIZE \ 322 ALIGN((HEAP_SYSTEM_S_SIZE + HEAP_SYS_RUNTIME_S_SIZE + SOF_STACK_SIZE),\ 323 SRAM_BANK_SIZE) 324 #define SOF_CORE_S_T_SIZE ((CONFIG_CORE_COUNT - 1) * SOF_CORE_S_SIZE) 325 326 /* 327 * The LP SRAM Heap and Stack on Cannonlake are organised like this :- 328 * 329 * +--------------------------------------------------------------------------+ 330 * | Offset | Region | Size | 331 * +---------------------+----------------+-----------------------------------+ 332 * | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE | 333 * | | Data | | 334 * | | BSS | | 335 * +---------------------+----------------+-----------------------------------+ 336 * | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE | 337 * +---------------------+----------------+-----------------------------------+ 338 * | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE | 339 * +---------------------+----------------+-----------------------------------+ 340 * | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE | 341 * +---------------------+----------------+-----------------------------------+ 342 * | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE | 343 * +---------------------+----------------+-----------------------------------+ 344 * | SOF_STACK_BASE | | | 345 * +---------------------+----------------+-----------------------------------+ 346 */ 347 348 /* LP SRAM */ 349 #define LP_SRAM_BASE 0xBE800000 350 351 /* Heap section sizes for module pool */ 352 #define HEAP_RT_LP_COUNT8 0 353 #define HEAP_RT_LP_COUNT16 256 354 #define HEAP_RT_LP_COUNT32 128 355 #define HEAP_RT_LP_COUNT64 64 356 #define HEAP_RT_LP_COUNT128 64 357 #define HEAP_RT_LP_COUNT256 96 358 #define HEAP_RT_LP_COUNT512 8 359 #define HEAP_RT_LP_COUNT1024 4 360 361 /* Heap configuration */ 362 #define SOF_LP_DATA_SIZE 0x4000 363 364 #define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE) 365 #define HEAP_LP_SYSTEM_SIZE 0x1000 366 367 #define HEAP_LP_RUNTIME_BASE \ 368 (HEAP_LP_SYSTEM_BASE + HEAP_LP_SYSTEM_SIZE) 369 #define HEAP_LP_RUNTIME_SIZE \ 370 (HEAP_RT_LP_COUNT8 * 8 + HEAP_RT_LP_COUNT16 * 16 + \ 371 HEAP_RT_LP_COUNT32 * 32 + HEAP_RT_LP_COUNT64 * 64 + \ 372 HEAP_RT_LP_COUNT128 * 128 + HEAP_RT_LP_COUNT256 * 256 + \ 373 HEAP_RT_LP_COUNT512 * 512 + HEAP_RT_LP_COUNT1024 * 1024) 374 375 #if (CONFIG_CAVS_LPS) 376 #define LPS_RESTORE_VECTOR_OFFSET 0x1000 377 #define LPS_RESTORE_VECTOR_SIZE 0x800 378 #define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET) 379 #define HEAP_LP_BUFFER_BASE (LPS_RESTORE_VECTOR_ADDR + LPS_RESTORE_VECTOR_SIZE) 380 #define HEAP_LP_BUFFER_SIZE (LP_SRAM_SIZE - LPS_RESTORE_VECTOR_SIZE -\ 381 LPS_RESTORE_VECTOR_OFFSET) 382 #else 383 #define HEAP_LP_BUFFER_BASE LP_SRAM_BASE 384 #define HEAP_LP_BUFFER_SIZE LP_SRAM_SIZE 385 #endif 386 387 #define HEAP_LP_BUFFER_BLOCK_SIZE 0x180 388 389 #if CONFIG_LP_MEMORY_BANKS 390 #define HEAP_LP_BUFFER_COUNT \ 391 (HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE) 392 #else 393 #define HEAP_LP_BUFFER_COUNT 0 394 #endif 395 396 #define PLATFORM_HEAP_SYSTEM CONFIG_CORE_COUNT /* one per core */ 397 #define PLATFORM_HEAP_SYSTEM_RUNTIME CONFIG_CORE_COUNT /* one per core */ 398 #define PLATFORM_HEAP_RUNTIME 1 399 #define PLATFORM_HEAP_RUNTIME_SHARED 1 400 #define PLATFORM_HEAP_SYSTEM_SHARED 1 401 #define PLATFORM_HEAP_BUFFER 2 402 403 /* Stack configuration */ 404 #define SOF_LP_STACK_SIZE 0x1000 405 #define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE) 406 #define SOF_LP_STACK_END (SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE) 407 408 /* Vector and literal sizes - do not use core-isa.h */ 409 #define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET 410 #define SOF_MEM_VECT_LIT_SIZE 0x8 411 #define SOF_MEM_VECT_TEXT_SIZE 0x38 412 #define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + \ 413 SOF_MEM_VECT_LIT_SIZE) 414 415 #define SOF_MEM_ERROR_TEXT_SIZE 0x180 416 #define SOF_MEM_ERROR_LIT_SIZE 0x8 417 418 #define SOF_MEM_RESET_TEXT_SIZE 0x268 419 #define SOF_MEM_RESET_LIT_SIZE 0x8 420 #define SOF_MEM_VECBASE_LIT_SIZE 0x178 421 422 #define SOF_MEM_RO_SIZE 0x8 423 424 /* VM ROM sizes */ 425 #define ROM_RESET_TEXT_SIZE 0x400 426 #define ROM_RESET_LIT_SIZE 0x200 427 428 /* boot loader in IMR */ 429 #define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 430 #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 431 432 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000 433 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120 434 #define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \ 435 IMR_BOOT_LDR_TEXT_ENTRY_SIZE) 436 #define IMR_BOOT_LDR_LIT_SIZE 0x22 437 #define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + \ 438 IMR_BOOT_LDR_LIT_SIZE) 439 #define IMR_BOOT_LDR_TEXT_SIZE 0x1C00 440 #define IMR_BOOT_LDR_DATA_BASE 0xB0039000 441 #define IMR_BOOT_LDR_DATA_SIZE 0x1000 442 #define IMR_BOOT_LDR_BSS_BASE 0xB0100000 443 #define IMR_BOOT_LDR_BSS_SIZE 0x10000 444 445 /* Temporary stack place for boot_ldr */ 446 #define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \ 447 SOF_STACK_TOTAL_SIZE) 448 #define BOOT_LDR_STACK_SIZE SOF_STACK_TOTAL_SIZE 449 450 /* L1 init */ 451 #define L1_CACHE_PREFCTL_VALUE 0x0000 452 453 #define host_to_local(addr) (addr) 454 #define local_to_host(addr) (addr) 455 456 #endif /* __PLATFORM_LIB_MEMORY_H__ */ 457 458 #else 459 460 #error "This file shouldn't be included from outside of sof/lib/memory.h" 461 462 #endif /* __SOF_LIB_MEMORY_H__ */ 463
