1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Cottonwood/Xtensa/SWConfig/hal/specreg.h.tpp#2 $ */ 6 7 /* Customer ID=11430; Build=0x668e9; Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #ifndef XTENSA_SPECREG_H 29 #define XTENSA_SPECREG_H 30 31 /* Include these special register bitfield definitions, for historical reasons: */ 32 #include <xtensa/corebits.h> 33 34 35 /* Special registers: */ 36 #define LBEG 0 37 #define LEND 1 38 #define LCOUNT 2 39 #define SAR 3 40 #define BR 4 41 #define SCOMPARE1 12 42 #define ACCLO 16 43 #define ACCHI 17 44 #define MR_0 32 45 #define MR_1 33 46 #define MR_2 34 47 #define MR_3 35 48 #define PREFCTL 40 49 #define WINDOWBASE 72 50 #define WINDOWSTART 73 51 #define IBREAKENABLE 96 52 #define ATOMCTL 99 53 #define DDR 104 54 #define IBREAKA_0 128 55 #define IBREAKA_1 129 56 #define DBREAKA_0 144 57 #define DBREAKA_1 145 58 #define DBREAKC_0 160 59 #define DBREAKC_1 161 60 #define EPC_1 177 61 #define EPC_2 178 62 #define EPC_3 179 63 #define EPC_4 180 64 #define EPC_5 181 65 #define EPC_6 182 66 #define EPC_7 183 67 #define DEPC 192 68 #define EPS_2 194 69 #define EPS_3 195 70 #define EPS_4 196 71 #define EPS_5 197 72 #define EPS_6 198 73 #define EPS_7 199 74 #define EXCSAVE_1 209 75 #define EXCSAVE_2 210 76 #define EXCSAVE_3 211 77 #define EXCSAVE_4 212 78 #define EXCSAVE_5 213 79 #define EXCSAVE_6 214 80 #define EXCSAVE_7 215 81 #define CPENABLE 224 82 #define INTERRUPT 226 83 #define INTENABLE 228 84 #define PS 230 85 #define VECBASE 231 86 #define EXCCAUSE 232 87 #define DEBUGCAUSE 233 88 #define CCOUNT 234 89 #define PRID 235 90 #define ICOUNT 236 91 #define ICOUNTLEVEL 237 92 #define EXCVADDR 238 93 #define CCOMPARE_0 240 94 #define CCOMPARE_1 241 95 #define CCOMPARE_2 242 96 97 /* Special cases (bases of special register series): */ 98 #define MR 32 99 #define IBREAKA 128 100 #define DBREAKA 144 101 #define DBREAKC 160 102 #define EPC 176 103 #define EPS 192 104 #define EXCSAVE 208 105 #define CCOMPARE 240 106 107 /* Special names for read-only and write-only interrupt registers: */ 108 #define INTREAD 226 109 #define INTSET 226 110 #define INTCLEAR 227 111 112 #endif /* XTENSA_SPECREG_H */ 113
