1# SPDX-License-Identifier: BSD-3-Clause
2
3config XT_WAITI_DELAY
4	bool
5	default n
6	help
7	  LX6 Xtensa platforms may require additional delay to flush loads
8	  and stores before entering WAITI.
9
10config HOST_PTABLE
11	bool
12	default n
13
14config XT_BOOT_LOADER
15	bool
16	default n
17
18config XT_HAVE_RESET_VECTOR_ROM
19	bool
20	default n
21	help
22	  Select if your platform has the reset vector
23	  in ROM.
24
25config XT_IRQ_MAP
26	bool
27	default n
28
29config DMA_GW
30	bool
31	default n
32
33config MEM_WND
34	bool
35	default n
36
37config INTEL_IOMUX
38	bool
39	default n
40
41config DMA_HW_LLI
42	bool
43	default n
44	help
45	  Hardware linked list is DMA feature, which allows
46	  to automatically reload the next programmed linked list
47	  item from memory without stopping the transfer. Without
48	  it the transfer stops after every lli read and FW needs
49	  to manually setup the next transfer.
50
51	  Any platforms with hardware linked list support
52	  should set this.
53
54config DMA_SUSPEND_DRAIN
55	bool
56	default n
57	help
58	  Some platforms cannot just simple disable DMA
59	  channel during the transfer, because it will
60	  hang the whole DMA controller. Instead we can
61	  suspend the channel and drain the FIFO in order
62	  to stop the channel as soon as possible.
63
64	  Any platforms without the ability to disable
65	  the DMA channel right away should set this.
66
67config DMA_FIFO_PARTITION
68	bool
69	default n
70	help
71	  Some platforms require to manually set DMA
72	  FIFO partitions before starting any transfer.
73
74	  Any platforms without automatic FIFO partitions
75	  should set this.
76
77config XT_INTERRUPT_LEVEL_1
78	bool
79	default n
80	help
81	  Select if the platform supports any interrupts of level 1.
82	  Disabling this option allows for less memory consumption.
83
84config XT_INTERRUPT_LEVEL_2
85	bool
86	default n
87	help
88	  Select if the platform supports any interrupts of level 2.
89	  Disabling this option allows for less memory consumption.
90
91config XT_INTERRUPT_LEVEL_3
92	bool
93	default n
94	help
95	  Select if the platform supports any interrupts of level 3.
96	  Disabling this option allows for less memory consumption.
97
98config XT_INTERRUPT_LEVEL_4
99	bool
100	default n
101	help
102	  Select if the platform supports any interrupts of level 4.
103	  Disabling this option allows for less memory consumption.
104
105config XT_INTERRUPT_LEVEL_5
106	bool
107	default n
108	help
109	  Select if the platform supports any interrupts of level 5.
110	  Disabling this option allows for less memory consumption.
111
112config COMPILER_WORKAROUND_CACHE_ATTR
113	bool
114	default n
115	help
116	  Select this to activate use of functions instead of macros
117	  to decide whether an address is cacheable or not.
118	  There is a weird optimization bug with gcc10x and gcc8.1
119	  (with -O2 flags) on IMX platforms. See PR #4605.
120
121rsource "src/Kconfig"
122
123# See zephyr/modules/Kconfig
124if !ZEPHYR_SOF_MODULE
125	rsource "Kconfig.xtos-build"
126endif
127
128menu "Debug"
129
130config DEBUG
131	bool "Enable debug build"
132	default n
133	help
134	  Select for debug build
135
136config GDB_DEBUG
137	bool "GDB Stub"
138	default n
139	help
140	  Select for GDB debugging
141
142config DEBUG_MEMORY_USAGE_SCAN
143	bool "Memory usage scan"
144	default y
145	help
146	  It enables memory usage scan at demand in runtime.
147	  This feature does not affect standard memory operations,
148	  especially allocation and deallocation.
149
150config DEBUG_LOCKS
151	bool "Spinlock debug"
152	default n
153	help
154	  It adds additional information to the spinlocks about
155	  the current user of the lock. Also executes panic
156	  on deadlock.
157
158config DEBUG_LOCKS_VERBOSE
159	bool "Spinlock verbose debug"
160	depends on DEBUG_LOCKS
161	default n
162	help
163	  In addition to DEBUG_LOCKS it also adds spinlock traces
164	  every time the lock is acquired.
165
166config DEBUG_IPC_COUNTERS
167	bool "IPC counters"
168	depends on CAVS
169	depends on DEBUG
170	default n
171	help
172	  Select for enabling tracing IPC counter in SRAM_REG mailbox
173
174config PERFORMANCE_COUNTERS
175	bool "Performance counters"
176	default n
177	help
178	  Enables tracing of simple performance measurements.
179	  A basic use case is to measure number of platform & cpu clock ticks
180	  passed between two checkpoints (init() and stamp()), for example
181	  total time spent on running low latency scheduler tasks.
182	  Platforms that gate cpu clock in wait-for-interrupt calls may also
183	  use the stamp() macro periodically to find out how long the cpu
184	  was in active/sleep state between the calls and estimate the cpu load.
185
186config DSP_RESIDENCY_COUNTERS
187	bool "DSP residency counters"
188	default n
189	help
190	  Enables simple DSP residency counters in SRAM_REG mailbox.
191	  R0, R1, R2 are abstract states which can be used differently
192	  based on platform implementation.
193
194if !ZEPHYR_SOF_MODULE
195	rsource "Kconfig.xtos-dbg"
196endif
197
198endmenu
199