1 /********************************************************************* 2 * SEGGER Microcontroller GmbH * 3 * The Embedded Experts * 4 ********************************************************************** 5 * * 6 * (c) 1995 - 2024 SEGGER Microcontroller GmbH * 7 * * 8 * www.segger.com Support: support@segger.com * 9 * * 10 ********************************************************************** 11 * * 12 * SEGGER SystemView * Real-time application analysis * 13 * * 14 ********************************************************************** 15 * * 16 * All rights reserved. * 17 * * 18 * SEGGER strongly recommends to not make any changes * 19 * to or modify the source code of this software in order to stay * 20 * compatible with the SystemView and RTT protocol, and J-Link. * 21 * * 22 * Redistribution and use in source and binary forms, with or * 23 * without modification, are permitted provided that the following * 24 * condition is met: * 25 * * 26 * o Redistributions of source code must retain the above copyright * 27 * notice, this condition and the following disclaimer. * 28 * * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 30 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 31 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 33 * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * 34 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 36 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 38 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 40 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 41 * DAMAGE. * 42 * * 43 ********************************************************************** 44 * * 45 * SystemView version: 3.58 * 46 * * 47 ********************************************************************** 48 ---------------------------END-OF-HEADER------------------------------ 49 File : SEGGER_RTT.h 50 Purpose : Implementation of SEGGER real-time transfer which allows 51 real-time communication on targets which support debugger 52 memory accesses while the CPU is running. 53 Revision: $Rev: 25842 $ 54 ---------------------------------------------------------------------- 55 */ 56 57 #ifndef SEGGER_RTT_H 58 #define SEGGER_RTT_H 59 60 #include "SEGGER_RTT_Conf.h" 61 62 /********************************************************************* 63 * 64 * Defines, defaults 65 * 66 ********************************************************************** 67 */ 68 69 #ifndef RTT_USE_ASM 70 // 71 // Some cores support out-of-order memory accesses (reordering of memory accesses in the core) 72 // For such cores, we need to define a memory barrier to guarantee the order of certain accesses to the RTT ring buffers. 73 // Needed for: 74 // Cortex-M7 (ARMv7-M) 75 // Cortex-M23 (ARM-v8M) 76 // Cortex-M33 (ARM-v8M) 77 // Cortex-A/R (ARM-v7A/R) 78 // 79 // We do not explicitly check for "Embedded Studio" as the compiler in use determines what we support. 80 // You can use an external toolchain like IAR inside ES. So there is no point in checking for "Embedded Studio" 81 // 82 #if (defined __CROSSWORKS_ARM) // Rowley Crossworks 83 #define _CC_HAS_RTT_ASM_SUPPORT 1 84 #if (defined __ARM_ARCH_7M__) // Cortex-M3 85 #define _CORE_HAS_RTT_ASM_SUPPORT 1 86 #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 87 #define _CORE_HAS_RTT_ASM_SUPPORT 1 88 #define _CORE_NEEDS_DMB 1 89 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 90 #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 91 #define _CORE_HAS_RTT_ASM_SUPPORT 0 92 #define _CORE_NEEDS_DMB 1 93 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 94 #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 95 #define _CORE_HAS_RTT_ASM_SUPPORT 1 96 #define _CORE_NEEDS_DMB 1 97 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 98 #elif (defined(__ARM_ARCH_8_1M_MAIN__)) // Cortex-M85 99 #define _CORE_HAS_RTT_ASM_SUPPORT 1 100 #define _CORE_NEEDS_DMB 1 101 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 102 #else 103 #define _CORE_HAS_RTT_ASM_SUPPORT 0 104 #endif 105 #elif (defined __ARMCC_VERSION) 106 // 107 // ARM compiler 108 // ARM compiler V6.0 and later is clang based. 109 // Our ASM part is compatible to clang. 110 // 111 #if (__ARMCC_VERSION >= 6000000) 112 #define _CC_HAS_RTT_ASM_SUPPORT 1 113 #else 114 #define _CC_HAS_RTT_ASM_SUPPORT 0 115 #endif 116 #if (defined __ARM_ARCH_6M__) // Cortex-M0 / M1 117 #define _CORE_HAS_RTT_ASM_SUPPORT 0 // No ASM support for this architecture 118 #elif (defined __ARM_ARCH_7M__) // Cortex-M3 119 #define _CORE_HAS_RTT_ASM_SUPPORT 1 120 #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 121 #define _CORE_HAS_RTT_ASM_SUPPORT 1 122 #define _CORE_NEEDS_DMB 1 123 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 124 #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 125 #define _CORE_HAS_RTT_ASM_SUPPORT 0 126 #define _CORE_NEEDS_DMB 1 127 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 128 #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 129 #define _CORE_HAS_RTT_ASM_SUPPORT 1 130 #define _CORE_NEEDS_DMB 1 131 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 132 #elif (defined __ARM_ARCH_8_1M_MAIN__) // Cortex-M85 133 #define _CORE_HAS_RTT_ASM_SUPPORT 1 134 #define _CORE_NEEDS_DMB 1 135 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 136 #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R 137 #define _CORE_NEEDS_DMB 1 138 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 139 #else 140 #define _CORE_HAS_RTT_ASM_SUPPORT 0 141 #endif 142 #elif ((defined __GNUC__) || (defined __clang__)) 143 // 144 // GCC / Clang 145 // 146 #define _CC_HAS_RTT_ASM_SUPPORT 1 147 // ARM 7/9: __ARM_ARCH_5__ / __ARM_ARCH_5E__ / __ARM_ARCH_5T__ / __ARM_ARCH_5T__ / __ARM_ARCH_5TE__ 148 #if (defined __ARM_ARCH_7M__) // Cortex-M3 149 #define _CORE_HAS_RTT_ASM_SUPPORT 1 150 #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 151 #define _CORE_HAS_RTT_ASM_SUPPORT 1 152 #define _CORE_NEEDS_DMB 1 // Only Cortex-M7 needs a DMB but we cannot distinguish M4 and M7 here... 153 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 154 #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 155 #define _CORE_HAS_RTT_ASM_SUPPORT 0 156 #define _CORE_NEEDS_DMB 1 157 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 158 #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 159 #define _CORE_HAS_RTT_ASM_SUPPORT 1 160 #define _CORE_NEEDS_DMB 1 161 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 162 #elif (defined __ARM_ARCH_8_1M_MAIN__) // Cortex-M85 163 #define _CORE_HAS_RTT_ASM_SUPPORT 1 164 #define _CORE_NEEDS_DMB 1 165 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 166 #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R 167 #define _CORE_NEEDS_DMB 1 168 #define RTT__DMB() __asm volatile ("dmb\n" : : :); 169 #else 170 #define _CORE_HAS_RTT_ASM_SUPPORT 0 171 #endif 172 #elif ((defined __IASMARM__) || (defined __ICCARM__)) 173 // 174 // IAR assembler/compiler 175 // 176 #define _CC_HAS_RTT_ASM_SUPPORT 1 177 #if (__VER__ < 6300000) 178 #define VOLATILE 179 #else 180 #define VOLATILE volatile 181 #endif 182 #if (defined __ARM7M__) // Needed for old versions that do not know the define yet 183 #if (__CORE__ == __ARM7M__) // Cortex-M3 184 #define _CORE_HAS_RTT_ASM_SUPPORT 1 185 #endif 186 #endif 187 #if (defined __ARM7EM__) 188 #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 189 #define _CORE_HAS_RTT_ASM_SUPPORT 1 190 #define _CORE_NEEDS_DMB 1 191 #define RTT__DMB() asm VOLATILE ("DMB"); 192 #endif 193 #endif 194 #if (defined __ARM8M_BASELINE__) 195 #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 196 #define _CORE_HAS_RTT_ASM_SUPPORT 0 197 #define _CORE_NEEDS_DMB 1 198 #define RTT__DMB() asm VOLATILE ("DMB"); 199 #endif 200 #endif 201 #if (defined __ARM8M_MAINLINE__) 202 #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 203 #define _CORE_HAS_RTT_ASM_SUPPORT 1 204 #define _CORE_NEEDS_DMB 1 205 #define RTT__DMB() asm VOLATILE ("DMB"); 206 #endif 207 #endif 208 #if (defined __ARM8EM_MAINLINE__) 209 #if (__CORE__ == __ARM8EM_MAINLINE__) // Cortex-??? 210 #define _CORE_HAS_RTT_ASM_SUPPORT 1 211 #define _CORE_NEEDS_DMB 1 212 #define RTT__DMB() asm VOLATILE ("DMB"); 213 #endif 214 #endif 215 #if (defined __ARM7A__) 216 #if (__CORE__ == __ARM7A__) // Cortex-A 32-bit ARMv7-A 217 #define _CORE_NEEDS_DMB 1 218 #define RTT__DMB() asm VOLATILE ("DMB"); 219 #endif 220 #endif 221 #if (defined __ARM7R__) 222 #if (__CORE__ == __ARM7R__) // Cortex-R 32-bit ARMv7-R 223 #define _CORE_NEEDS_DMB 1 224 #define RTT__DMB() asm VOLATILE ("DMB"); 225 #endif 226 #endif 227 // TBD: __ARM8A__ => Cortex-A 64-bit ARMv8-A 228 // TBD: __ARM8R__ => Cortex-R 64-bit ARMv8-R 229 #else 230 // 231 // Other compilers 232 // 233 #define _CC_HAS_RTT_ASM_SUPPORT 0 234 #define _CORE_HAS_RTT_ASM_SUPPORT 0 235 #endif 236 // 237 // If IDE and core support the ASM version, enable ASM version by default 238 // 239 #ifndef _CORE_HAS_RTT_ASM_SUPPORT 240 #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores 241 #endif 242 #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) 243 #define RTT_USE_ASM (1) 244 #else 245 #define RTT_USE_ASM (0) 246 #endif 247 #endif 248 249 #ifndef _CORE_NEEDS_DMB 250 #define _CORE_NEEDS_DMB 0 251 #endif 252 253 #ifndef RTT__DMB 254 #if _CORE_NEEDS_DMB 255 #error "Don't know how to place inline assembly for DMB" 256 #else 257 #define RTT__DMB() 258 #endif 259 #endif 260 261 #ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE 262 #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0) // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here 263 #endif 264 265 #ifndef SEGGER_RTT_UNCACHED_OFF 266 #if SEGGER_RTT_CPU_CACHE_LINE_SIZE 267 #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" 268 #else 269 #define SEGGER_RTT_UNCACHED_OFF (0) 270 #endif 271 #endif 272 #if RTT_USE_ASM 273 #if SEGGER_RTT_CPU_CACHE_LINE_SIZE 274 #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" 275 #endif 276 #endif 277 278 #ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file 279 #include <stdlib.h> 280 #include <stdarg.h> 281 #include <stdint.h> 282 283 /********************************************************************* 284 * 285 * Defines, fixed 286 * 287 ********************************************************************** 288 */ 289 290 // 291 // Determine how much we must pad the control block to make it a multiple of a cache line in size 292 // Assuming: U8 = 1B 293 // U16 = 2B 294 // U32 = 4B 295 // U8/U16/U32* = 4B 296 // 297 #if SEGGER_RTT_CPU_CACHE_LINE_SIZE // Avoid division by zero in case we do not have any cache 298 #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE) 299 #else 300 #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes) 301 #endif 302 #define SEGGER_RTT__CB_SIZE (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24)) 303 #define SEGGER_RTT__CB_PADDING (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE) 304 305 /********************************************************************* 306 * 307 * Types 308 * 309 ********************************************************************** 310 */ 311 312 // 313 // Description for a circular buffer (also called "ring buffer") 314 // which is used as up-buffer (T->H) 315 // 316 typedef struct { 317 const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" 318 char* pBuffer; // Pointer to start of buffer 319 unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. 320 unsigned WrOff; // Position of next item to be written by either target. 321 volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. 322 unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. 323 } SEGGER_RTT_BUFFER_UP; 324 325 // 326 // Description for a circular buffer (also called "ring buffer") 327 // which is used as down-buffer (H->T) 328 // 329 typedef struct { 330 const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" 331 char* pBuffer; // Pointer to start of buffer 332 unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. 333 volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. 334 unsigned RdOff; // Position of next item to be read by target (down-buffer). 335 unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. 336 } SEGGER_RTT_BUFFER_DOWN; 337 338 // 339 // RTT control block which describes the number of buffers available 340 // as well as the configuration for each buffer 341 // 342 // 343 typedef struct { 344 char acID[16]; // Initialized to "SEGGER RTT" 345 int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) 346 int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) 347 SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host 348 SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target 349 #if SEGGER_RTT__CB_PADDING 350 unsigned char aDummy[SEGGER_RTT__CB_PADDING]; 351 #endif 352 } SEGGER_RTT_CB; 353 354 /********************************************************************* 355 * 356 * Global data 357 * 358 ********************************************************************** 359 */ 360 extern SEGGER_RTT_CB _SEGGER_RTT; 361 362 /********************************************************************* 363 * 364 * RTT API functions 365 * 366 ********************************************************************** 367 */ 368 #ifdef __cplusplus 369 extern "C" { 370 #endif 371 int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); 372 int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); 373 int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); 374 int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); 375 int SEGGER_RTT_GetKey (void); 376 unsigned SEGGER_RTT_HasData (unsigned BufferIndex); 377 int SEGGER_RTT_HasKey (void); 378 unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex); 379 void SEGGER_RTT_Init (void); 380 unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); 381 unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); 382 int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); 383 int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); 384 int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); 385 int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); 386 int SEGGER_RTT_WaitKey (void); 387 unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); 388 unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); 389 unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); 390 unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); 391 unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); 392 void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); 393 unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); 394 unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); 395 unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); 396 unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex); 397 unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex); 398 // 399 // Function macro for performance optimization 400 // 401 #define SEGGER_RTT_HASDATA(n) (((SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) 402 403 #if RTT_USE_ASM 404 #define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock 405 #endif 406 407 /********************************************************************* 408 * 409 * RTT transfer functions to send RTT data via other channels. 410 * 411 ********************************************************************** 412 */ 413 unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); 414 unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); 415 unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); 416 unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); 417 418 #define SEGGER_RTT_HASDATA_UP(n) (((SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly 419 420 /********************************************************************* 421 * 422 * RTT "Terminal" API functions 423 * 424 ********************************************************************** 425 */ 426 int SEGGER_RTT_SetTerminal (unsigned char TerminalId); 427 int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s); 428 429 /********************************************************************* 430 * 431 * RTT printf functions (require SEGGER_RTT_printf.c) 432 * 433 ********************************************************************** 434 */ 435 int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); 436 int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); 437 438 #ifdef __cplusplus 439 } 440 #endif 441 442 #endif // ifndef(SEGGER_RTT_ASM) 443 444 // 445 // For some environments, NULL may not be defined until certain headers are included 446 // 447 #ifndef NULL 448 #define NULL ((void*)0) 449 #endif 450 451 /********************************************************************* 452 * 453 * Defines 454 * 455 ********************************************************************** 456 */ 457 458 // 459 // Operating modes. Define behavior if buffer is full (not enough space for entire message) 460 // 461 #define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) 462 #define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. 463 #define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. 464 #define SEGGER_RTT_MODE_MASK (3) 465 466 // 467 // Control sequences, based on ANSI. 468 // Can be used to control color, and clear the screen 469 // 470 #define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors 471 #define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left 472 473 #define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" 474 #define RTT_CTRL_TEXT_RED "\x1B[2;31m" 475 #define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" 476 #define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" 477 #define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" 478 #define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" 479 #define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" 480 #define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" 481 482 #define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" 483 #define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" 484 #define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" 485 #define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" 486 #define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" 487 #define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" 488 #define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" 489 #define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" 490 491 #define RTT_CTRL_BG_BLACK "\x1B[24;40m" 492 #define RTT_CTRL_BG_RED "\x1B[24;41m" 493 #define RTT_CTRL_BG_GREEN "\x1B[24;42m" 494 #define RTT_CTRL_BG_YELLOW "\x1B[24;43m" 495 #define RTT_CTRL_BG_BLUE "\x1B[24;44m" 496 #define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" 497 #define RTT_CTRL_BG_CYAN "\x1B[24;46m" 498 #define RTT_CTRL_BG_WHITE "\x1B[24;47m" 499 500 #define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" 501 #define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" 502 #define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" 503 #define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" 504 #define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" 505 #define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" 506 #define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" 507 #define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" 508 509 510 #endif 511 512 /*************************** End of file ****************************/ 513
