1 /********************************************************************* 2 * SEGGER Microcontroller GmbH * 3 * The Embedded Experts * 4 ********************************************************************** 5 * * 6 * (c) 1995 - 2021 SEGGER Microcontroller GmbH * 7 * * 8 * www.segger.com Support: support@segger.com * 9 * * 10 ********************************************************************** 11 * * 12 * SEGGER SystemView * Real-time application analysis * 13 * * 14 ********************************************************************** 15 * * 16 * All rights reserved. * 17 * * 18 * SEGGER strongly recommends to not make any changes * 19 * to or modify the source code of this software in order to stay * 20 * compatible with the SystemView and RTT protocol, and J-Link. * 21 * * 22 * Redistribution and use in source and binary forms, with or * 23 * without modification, are permitted provided that the following * 24 * condition is met: * 25 * * 26 * o Redistributions of source code must retain the above copyright * 27 * notice, this condition and the following disclaimer. * 28 * * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 30 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 31 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 33 * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * 34 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 36 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 38 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 40 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 41 * DAMAGE. * 42 * * 43 ********************************************************************** 44 * * 45 * SystemView version: 3.40 * 46 * * 47 ********************************************************************** 48 ---------------------------END-OF-HEADER------------------------------ 49 File : SEGGER_RTT_Conf.h 50 Purpose : Implementation of SEGGER real-time transfer (RTT) which 51 allows real-time communication on targets which support 52 debugger memory accesses while the CPU is running. 53 Revision: $Rev: 24316 $ 54 55 */ 56 57 #ifndef SEGGER_RTT_CONF_H 58 #define SEGGER_RTT_CONF_H 59 60 #ifdef __IAR_SYSTEMS_ICC__ 61 #include <intrinsics.h> 62 #endif 63 64 /********************************************************************* 65 * 66 * Defines, configurable 67 * 68 ********************************************************************** 69 */ 70 71 // 72 // Take in and set to correct values for Cortex-A systems with CPU cache 73 // 74 //#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system 75 //#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached 76 // 77 // Most common case: 78 // Up-channel 0: RTT 79 // Up-channel 1: SystemView 80 // 81 #define SEGGER_RTT_MAX_NUM_UP_BUFFERS CONFIG_SEGGER_RTT_MAX_NUM_UP_BUFFERS // Max. number of up-buffers (T->H) available on this target (Default: 3) 82 // 83 // Most common case: 84 // Down-channel 0: RTT 85 // Down-channel 1: SystemView 86 // 87 #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS CONFIG_SEGGER_RTT_MAX_NUM_DOWN_BUFFERS // Max. number of down-buffers (H->T) available on this target (Default: 3) 88 89 #define BUFFER_SIZE_UP CONFIG_SEGGER_RTT_BUFFER_SIZE_UP // Size of the buffer for terminal output of target, up to host (Default: 1k) 90 91 #define BUFFER_SIZE_DOWN CONFIG_SEGGER_RTT_BUFFER_SIZE_DOWN // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) 92 93 #define SEGGER_RTT_PRINTF_BUFFER_SIZE CONFIG_SEGGER_RTT_PRINTF_BUFFER_SIZE // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) 94 95 #define SEGGER_RTT_MODE_DEFAULT CONFIG_SEGGER_RTT_MODE // Mode for pre-initialized terminal channel (buffer 0) 96 97 #if defined(CONFIG_SEGGER_RTT_SECTION_DTCM) 98 #define SEGGER_RTT_SECTION ".dtcm_data" 99 #elif defined(CONFIG_SEGGER_RTT_SECTION_CCM) 100 #define SEGGER_RTT_SECTION ".ccm_data" 101 #elif defined(CONFIG_SEGGER_RTT_SECTION_CUSTOM) 102 #define SEGGER_RTT_SECTION CONFIG_SEGGER_RTT_SECTION_CUSTOM_NAME 103 #endif 104 105 /********************************************************************* 106 * 107 * RTT memcpy configuration 108 * 109 * memcpy() is good for large amounts of data, 110 * but the overhead is big for small amounts, which are usually stored via RTT. 111 * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. 112 * 113 * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. 114 * This is may be required with memory access restrictions, 115 * such as on Cortex-A devices with MMU. 116 */ 117 #if defined(CONFIG_SEGGER_RTT_MEMCPY_USE_BYTELOOP) 118 #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 1 // 1: Use a simple byte-loop 119 #else 120 #ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP 121 #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY 122 #endif 123 #endif 124 // 125 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets 126 // 127 //#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) 128 // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) 129 //#endif 130 131 // 132 // Target is not allowed to perform other RTT operations while string still has not been stored completely. 133 // Otherwise we would probably end up with a mixed string in the buffer. 134 // If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. 135 // 136 // SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. 137 // Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. 138 // When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. 139 // (Higher priority = lower priority number) 140 // Default value for embOS: 128u 141 // Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) 142 // In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC 143 // or define SEGGER_RTT_LOCK() to completely disable interrupts. 144 // 145 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 146 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) 147 #endif 148 149 /********************************************************************* 150 * 151 * RTT lock configuration for SEGGER Embedded Studio, 152 * Rowley CrossStudio and GCC 153 */ 154 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) 155 #if defined(__ZEPHYR__) && defined (CONFIG_SEGGER_RTT_CUSTOM_LOCKING) 156 extern unsigned int zephyr_rtt_irq_lock(void); 157 extern void zephyr_rtt_irq_unlock(unsigned int key); 158 #define SEGGER_RTT_LOCK() { \ 159 unsigned int key = zephyr_rtt_irq_lock() 160 #define SEGGER_RTT_UNLOCK() zephyr_rtt_irq_unlock(key); \ 161 } 162 #define RTT_USE_ASM 0 163 #elif (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) 164 #define SEGGER_RTT_LOCK() { \ 165 unsigned int _SEGGER_RTT__LockState; \ 166 __asm volatile ("mrs %0, primask \n\t" \ 167 "movs r1, #1 \n\t" \ 168 "msr primask, r1 \n\t" \ 169 : "=r" (_SEGGER_RTT__LockState) \ 170 : \ 171 : "r1", "cc" \ 172 ); 173 174 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ 175 : \ 176 : "r" (_SEGGER_RTT__LockState) \ 177 : \ 178 ); \ 179 } 180 #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) 181 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 182 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 183 #endif 184 #define SEGGER_RTT_LOCK() { \ 185 unsigned int _SEGGER_RTT__LockState; \ 186 __asm volatile ("mrs %0, basepri \n\t" \ 187 "mov r1, %1 \n\t" \ 188 "msr basepri, r1 \n\t" \ 189 : "=r" (_SEGGER_RTT__LockState) \ 190 : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ 191 : "r1", "cc" \ 192 ); 193 194 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ 195 : \ 196 : "r" (_SEGGER_RTT__LockState) \ 197 : \ 198 ); \ 199 } 200 201 #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) 202 #define SEGGER_RTT_LOCK() { \ 203 unsigned int _SEGGER_RTT__LockState; \ 204 __asm volatile ("mrs r1, CPSR \n\t" \ 205 "mov %0, r1 \n\t" \ 206 "orr r1, r1, #0xC0 \n\t" \ 207 "msr CPSR_c, r1 \n\t" \ 208 : "=r" (_SEGGER_RTT__LockState) \ 209 : \ 210 : "r1", "cc" \ 211 ); 212 213 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ 214 "mrs r1, CPSR \n\t" \ 215 "bic r1, r1, #0xC0 \n\t" \ 216 "and r0, r0, #0xC0 \n\t" \ 217 "orr r1, r1, r0 \n\t" \ 218 "msr CPSR_c, r1 \n\t" \ 219 : \ 220 : "r" (_SEGGER_RTT__LockState) \ 221 : "r0", "r1", "cc" \ 222 ); \ 223 } 224 #elif defined(__riscv) || defined(__riscv_xlen) 225 #define SEGGER_RTT_LOCK() { \ 226 unsigned int _SEGGER_RTT__LockState; \ 227 __asm volatile ("csrr %0, mstatus \n\t" \ 228 "csrci mstatus, 8 \n\t" \ 229 "andi %0, %0, 8 \n\t" \ 230 : "=r" (_SEGGER_RTT__LockState) \ 231 : \ 232 : \ 233 ); 234 235 #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ 236 "or %0, %0, a1 \n\t" \ 237 "csrs mstatus, %0 \n\t" \ 238 : \ 239 : "r" (_SEGGER_RTT__LockState) \ 240 : "a1" \ 241 ); \ 242 } 243 #else 244 #define SEGGER_RTT_LOCK() 245 #define SEGGER_RTT_UNLOCK() 246 #endif 247 #endif 248 249 /********************************************************************* 250 * 251 * RTT lock configuration for IAR EWARM 252 */ 253 #ifdef __ICCARM__ 254 #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ 255 (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) 256 #define SEGGER_RTT_LOCK() { \ 257 unsigned int _SEGGER_RTT__LockState; \ 258 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 259 __set_PRIMASK(1); 260 261 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ 262 } 263 #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ 264 (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ 265 (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ 266 (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) 267 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 268 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 269 #endif 270 #define SEGGER_RTT_LOCK() { \ 271 unsigned int _SEGGER_RTT__LockState; \ 272 _SEGGER_RTT__LockState = __get_BASEPRI(); \ 273 __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 274 275 #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ 276 } 277 #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ 278 (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) 279 #define SEGGER_RTT_LOCK() { \ 280 unsigned int _SEGGER_RTT__LockState; \ 281 __asm volatile ("mrs r1, CPSR \n\t" \ 282 "mov %0, r1 \n\t" \ 283 "orr r1, r1, #0xC0 \n\t" \ 284 "msr CPSR_c, r1 \n\t" \ 285 : "=r" (_SEGGER_RTT__LockState) \ 286 : \ 287 : "r1", "cc" \ 288 ); 289 290 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ 291 "mrs r1, CPSR \n\t" \ 292 "bic r1, r1, #0xC0 \n\t" \ 293 "and r0, r0, #0xC0 \n\t" \ 294 "orr r1, r1, r0 \n\t" \ 295 "msr CPSR_c, r1 \n\t" \ 296 : \ 297 : "r" (_SEGGER_RTT__LockState) \ 298 : "r0", "r1", "cc" \ 299 ); \ 300 } 301 #endif 302 #endif 303 304 /********************************************************************* 305 * 306 * RTT lock configuration for IAR RX 307 */ 308 #ifdef __ICCRX__ 309 #define SEGGER_RTT_LOCK() { \ 310 unsigned long _SEGGER_RTT__LockState; \ 311 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 312 __disable_interrupt(); 313 314 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ 315 } 316 #endif 317 318 /********************************************************************* 319 * 320 * RTT lock configuration for IAR RL78 321 */ 322 #ifdef __ICCRL78__ 323 #define SEGGER_RTT_LOCK() { \ 324 __istate_t _SEGGER_RTT__LockState; \ 325 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 326 __disable_interrupt(); 327 328 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ 329 } 330 #endif 331 332 /********************************************************************* 333 * 334 * RTT lock configuration for KEIL ARM 335 */ 336 #ifdef __CC_ARM 337 #if (defined __TARGET_ARCH_6S_M) 338 #define SEGGER_RTT_LOCK() { \ 339 unsigned int _SEGGER_RTT__LockState; \ 340 register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ 341 _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ 342 _SEGGER_RTT__PRIMASK = 1u; \ 343 __schedule_barrier(); 344 345 #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ 346 __schedule_barrier(); \ 347 } 348 #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) 349 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 350 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 351 #endif 352 #define SEGGER_RTT_LOCK() { \ 353 unsigned int _SEGGER_RTT__LockState; \ 354 register unsigned char BASEPRI __asm( "basepri"); \ 355 _SEGGER_RTT__LockState = BASEPRI; \ 356 BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ 357 __schedule_barrier(); 358 359 #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ 360 __schedule_barrier(); \ 361 } 362 #endif 363 #endif 364 365 /********************************************************************* 366 * 367 * RTT lock configuration for TI ARM 368 */ 369 #ifdef __TI_ARM__ 370 #if defined (__TI_ARM_V6M0__) 371 #define SEGGER_RTT_LOCK() { \ 372 unsigned int _SEGGER_RTT__LockState; \ 373 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 374 __set_PRIMASK(1); 375 376 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ 377 } 378 #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) 379 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 380 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 381 #endif 382 #define SEGGER_RTT_LOCK() { \ 383 unsigned int _SEGGER_RTT__LockState; \ 384 _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 385 386 #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ 387 } 388 #endif 389 #endif 390 391 /********************************************************************* 392 * 393 * RTT lock configuration for CCRX 394 */ 395 #ifdef __RX 396 #include <machine.h> 397 #define SEGGER_RTT_LOCK() { \ 398 unsigned long _SEGGER_RTT__LockState; \ 399 _SEGGER_RTT__LockState = get_psw() & 0x010000; \ 400 clrpsw_i(); 401 402 #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ 403 } 404 #endif 405 406 /********************************************************************* 407 * 408 * RTT lock configuration for embOS Simulation on Windows 409 * (Can also be used for generic RTT locking with embOS) 410 */ 411 #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) 412 413 void OS_SIM_EnterCriticalSection(void); 414 void OS_SIM_LeaveCriticalSection(void); 415 416 #define SEGGER_RTT_LOCK() { \ 417 OS_SIM_EnterCriticalSection(); 418 419 #define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ 420 } 421 #endif 422 423 /********************************************************************* 424 * 425 * RTT lock configuration fallback 426 */ 427 #ifndef SEGGER_RTT_LOCK 428 #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) 429 #endif 430 431 #ifndef SEGGER_RTT_UNLOCK 432 #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) 433 #endif 434 435 #endif 436 /*************************** End of file ****************************/ 437
