1 /********************************************************************* 2 * SEGGER Microcontroller GmbH * 3 * The Embedded Experts * 4 ********************************************************************** 5 * * 6 * (c) 1995 - 2021 SEGGER Microcontroller GmbH * 7 * * 8 * www.segger.com Support: support@segger.com * 9 * * 10 ********************************************************************** 11 * * 12 * SEGGER SystemView * Real-time application analysis * 13 * * 14 ********************************************************************** 15 * * 16 * All rights reserved. * 17 * * 18 * SEGGER strongly recommends to not make any changes * 19 * to or modify the source code of this software in order to stay * 20 * compatible with the SystemView and RTT protocol, and J-Link. * 21 * * 22 * Redistribution and use in source and binary forms, with or * 23 * without modification, are permitted provided that the following * 24 * condition is met: * 25 * * 26 * o Redistributions of source code must retain the above copyright * 27 * notice, this condition and the following disclaimer. * 28 * * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 30 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 31 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 33 * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * 34 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 36 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 38 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 40 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 41 * DAMAGE. * 42 * * 43 ********************************************************************** 44 * * 45 * SystemView version: 3.30 * 46 * * 47 ********************************************************************** 48 ---------------------------END-OF-HEADER------------------------------ 49 File : SEGGER_RTT_Conf.h 50 Purpose : Implementation of SEGGER real-time transfer (RTT) which 51 allows real-time communication on targets which support 52 debugger memory accesses while the CPU is running. 53 Revision: $Rev: 21386 $ 54 55 */ 56 57 #ifndef SEGGER_RTT_CONF_H 58 #define SEGGER_RTT_CONF_H 59 60 #ifdef __IAR_SYSTEMS_ICC__ 61 #include <intrinsics.h> 62 #endif 63 64 /********************************************************************* 65 * 66 * Defines, configurable 67 * 68 ********************************************************************** 69 */ 70 71 // 72 // Take in and set to correct values for Cortex-A systems with CPU cache 73 // 74 //#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system 75 //#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached 76 // 77 // Most common case: 78 // Up-channel 0: RTT 79 // Up-channel 1: SystemView 80 // 81 #define SEGGER_RTT_MAX_NUM_UP_BUFFERS CONFIG_SEGGER_RTT_MAX_NUM_UP_BUFFERS // Max. number of up-buffers (T->H) available on this target (Default: 3) 82 // 83 // Most common case: 84 // Down-channel 0: RTT 85 // Down-channel 1: SystemView 86 // 87 #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS CONFIG_SEGGER_RTT_MAX_NUM_DOWN_BUFFERS // Max. number of down-buffers (H->T) available on this target (Default: 3) 88 89 #define BUFFER_SIZE_UP CONFIG_SEGGER_RTT_BUFFER_SIZE_UP // Size of the buffer for terminal output of target, up to host (Default: 1k) 90 91 #define BUFFER_SIZE_DOWN CONFIG_SEGGER_RTT_BUFFER_SIZE_DOWN // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) 92 93 #define SEGGER_RTT_PRINTF_BUFFER_SIZE CONFIG_SEGGER_RTT_PRINTF_BUFFER_SIZE // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) 94 95 #define SEGGER_RTT_MODE_DEFAULT CONFIG_SEGGER_RTT_MODE // Mode for pre-initialized terminal channel (buffer 0) 96 97 #if defined(CONFIG_SEGGER_RTT_SECTION_DTCM) 98 #define SEGGER_RTT_SECTION ".dtcm_data" 99 #endif 100 101 /********************************************************************* 102 * 103 * RTT memcpy configuration 104 * 105 * memcpy() is good for large amounts of data, 106 * but the overhead is big for small amounts, which are usually stored via RTT. 107 * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. 108 * 109 * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. 110 * This is may be required with memory access restrictions, 111 * such as on Cortex-A devices with MMU. 112 */ 113 #if defined(CONFIG_SEGGER_RTT_MEMCPY_USE_BYTELOOP) 114 #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 1 // 1: Use a simple byte-loop 115 #else 116 #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY 117 #endif 118 // 119 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets 120 // 121 //#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) 122 // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) 123 //#endif 124 125 // 126 // Target is not allowed to perform other RTT operations while string still has not been stored completely. 127 // Otherwise we would probably end up with a mixed string in the buffer. 128 // If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. 129 // 130 // SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. 131 // Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. 132 // When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. 133 // (Higher priority = lower priority number) 134 // Default value for embOS: 128u 135 // Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) 136 // In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC 137 // or define SEGGER_RTT_LOCK() to completely disable interrupts. 138 // 139 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 140 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) 141 #endif 142 143 /********************************************************************* 144 * 145 * RTT lock configuration for SEGGER Embedded Studio, 146 * Rowley CrossStudio and GCC 147 */ 148 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) 149 #if defined(__ZEPHYR__) && defined (CONFIG_SEGGER_RTT_CUSTOM_LOCKING) 150 #ifdef CONFIG_MULTITHREADING 151 extern void zephyr_rtt_mutex_lock(void); 152 extern void zephyr_rtt_mutex_unlock(void); 153 #define SEGGER_RTT_LOCK() zephyr_rtt_mutex_lock() 154 #define SEGGER_RTT_UNLOCK() zephyr_rtt_mutex_unlock() 155 #else 156 extern unsigned int zephyr_rtt_irq_lock(void); 157 extern void zephyr_rtt_irq_unlock(unsigned int key); 158 #define SEGGER_RTT_LOCK() { \ 159 unsigned int key = zephyr_rtt_irq_lock() 160 #define SEGGER_RTT_UNLOCK() zephyr_rtt_irq_unlock(key); \ 161 } 162 #endif 163 #define RTT_USE_ASM 0 164 #elif (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) 165 #define SEGGER_RTT_LOCK() { \ 166 unsigned int _SEGGER_RTT__LockState; \ 167 __asm volatile ("mrs %0, primask \n\t" \ 168 "movs r1, #1 \n\t" \ 169 "msr primask, r1 \n\t" \ 170 : "=r" (_SEGGER_RTT__LockState) \ 171 : \ 172 : "r1", "cc" \ 173 ); 174 175 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ 176 : \ 177 : "r" (_SEGGER_RTT__LockState) \ 178 : \ 179 ); \ 180 } 181 #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) 182 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 183 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 184 #endif 185 #define SEGGER_RTT_LOCK() { \ 186 unsigned int _SEGGER_RTT__LockState; \ 187 __asm volatile ("mrs %0, basepri \n\t" \ 188 "mov r1, %1 \n\t" \ 189 "msr basepri, r1 \n\t" \ 190 : "=r" (_SEGGER_RTT__LockState) \ 191 : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ 192 : "r1", "cc" \ 193 ); 194 195 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ 196 : \ 197 : "r" (_SEGGER_RTT__LockState) \ 198 : \ 199 ); \ 200 } 201 202 #elif defined(__ARM_ARCH_7A__) 203 #define SEGGER_RTT_LOCK() { \ 204 unsigned int _SEGGER_RTT__LockState; \ 205 __asm volatile ("mrs r1, CPSR \n\t" \ 206 "mov %0, r1 \n\t" \ 207 "orr r1, r1, #0xC0 \n\t" \ 208 "msr CPSR_c, r1 \n\t" \ 209 : "=r" (_SEGGER_RTT__LockState) \ 210 : \ 211 : "r1", "cc" \ 212 ); 213 214 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ 215 "mrs r1, CPSR \n\t" \ 216 "bic r1, r1, #0xC0 \n\t" \ 217 "and r0, r0, #0xC0 \n\t" \ 218 "orr r1, r1, r0 \n\t" \ 219 "msr CPSR_c, r1 \n\t" \ 220 : \ 221 : "r" (_SEGGER_RTT__LockState) \ 222 : "r0", "r1", "cc" \ 223 ); \ 224 } 225 #elif defined(__riscv) || defined(__riscv_xlen) 226 #define SEGGER_RTT_LOCK() { \ 227 unsigned int _SEGGER_RTT__LockState; \ 228 __asm volatile ("csrr %0, mstatus \n\t" \ 229 "csrci mstatus, 8 \n\t" \ 230 "andi %0, %0, 8 \n\t" \ 231 : "=r" (_SEGGER_RTT__LockState) \ 232 : \ 233 : \ 234 ); 235 236 #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ 237 "or %0, %0, a1 \n\t" \ 238 "csrs mstatus, %0 \n\t" \ 239 : \ 240 : "r" (_SEGGER_RTT__LockState) \ 241 : "a1" \ 242 ); \ 243 } 244 #else 245 #define SEGGER_RTT_LOCK() 246 #define SEGGER_RTT_UNLOCK() 247 #endif 248 #endif 249 250 /********************************************************************* 251 * 252 * RTT lock configuration for IAR EWARM 253 */ 254 #ifdef __ICCARM__ 255 #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ 256 (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) 257 #define SEGGER_RTT_LOCK() { \ 258 unsigned int _SEGGER_RTT__LockState; \ 259 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 260 __set_PRIMASK(1); 261 262 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ 263 } 264 #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ 265 (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ 266 (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ 267 (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) 268 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 269 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 270 #endif 271 #define SEGGER_RTT_LOCK() { \ 272 unsigned int _SEGGER_RTT__LockState; \ 273 _SEGGER_RTT__LockState = __get_BASEPRI(); \ 274 __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 275 276 #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ 277 } 278 #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ 279 (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) 280 #define SEGGER_RTT_LOCK() { \ 281 unsigned int _SEGGER_RTT__LockState; \ 282 __asm volatile ("mrs r1, CPSR \n\t" \ 283 "mov %0, r1 \n\t" \ 284 "orr r1, r1, #0xC0 \n\t" \ 285 "msr CPSR_c, r1 \n\t" \ 286 : "=r" (_SEGGER_RTT__LockState) \ 287 : \ 288 : "r1", "cc" \ 289 ); 290 291 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ 292 "mrs r1, CPSR \n\t" \ 293 "bic r1, r1, #0xC0 \n\t" \ 294 "and r0, r0, #0xC0 \n\t" \ 295 "orr r1, r1, r0 \n\t" \ 296 "msr CPSR_c, r1 \n\t" \ 297 : \ 298 : "r" (_SEGGER_RTT__LockState) \ 299 : "r0", "r1", "cc" \ 300 ); \ 301 } 302 #endif 303 #endif 304 305 /********************************************************************* 306 * 307 * RTT lock configuration for IAR RX 308 */ 309 #ifdef __ICCRX__ 310 #define SEGGER_RTT_LOCK() { \ 311 unsigned long _SEGGER_RTT__LockState; \ 312 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 313 __disable_interrupt(); 314 315 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ 316 } 317 #endif 318 319 /********************************************************************* 320 * 321 * RTT lock configuration for IAR RL78 322 */ 323 #ifdef __ICCRL78__ 324 #define SEGGER_RTT_LOCK() { \ 325 __istate_t _SEGGER_RTT__LockState; \ 326 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 327 __disable_interrupt(); 328 329 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ 330 } 331 #endif 332 333 /********************************************************************* 334 * 335 * RTT lock configuration for KEIL ARM 336 */ 337 #ifdef __CC_ARM 338 #if (defined __TARGET_ARCH_6S_M) 339 #define SEGGER_RTT_LOCK() { \ 340 unsigned int _SEGGER_RTT__LockState; \ 341 register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ 342 _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ 343 _SEGGER_RTT__PRIMASK = 1u; \ 344 __schedule_barrier(); 345 346 #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ 347 __schedule_barrier(); \ 348 } 349 #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) 350 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 351 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 352 #endif 353 #define SEGGER_RTT_LOCK() { \ 354 unsigned int _SEGGER_RTT__LockState; \ 355 register unsigned char BASEPRI __asm( "basepri"); \ 356 _SEGGER_RTT__LockState = BASEPRI; \ 357 BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ 358 __schedule_barrier(); 359 360 #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ 361 __schedule_barrier(); \ 362 } 363 #endif 364 #endif 365 366 /********************************************************************* 367 * 368 * RTT lock configuration for TI ARM 369 */ 370 #ifdef __TI_ARM__ 371 #if defined (__TI_ARM_V6M0__) 372 #define SEGGER_RTT_LOCK() { \ 373 unsigned int _SEGGER_RTT__LockState; \ 374 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 375 __set_PRIMASK(1); 376 377 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ 378 } 379 #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) 380 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 381 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 382 #endif 383 #define SEGGER_RTT_LOCK() { \ 384 unsigned int _SEGGER_RTT__LockState; \ 385 _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 386 387 #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ 388 } 389 #endif 390 #endif 391 392 /********************************************************************* 393 * 394 * RTT lock configuration for CCRX 395 */ 396 #ifdef __RX 397 #include <machine.h> 398 #define SEGGER_RTT_LOCK() { \ 399 unsigned long _SEGGER_RTT__LockState; \ 400 _SEGGER_RTT__LockState = get_psw() & 0x010000; \ 401 clrpsw_i(); 402 403 #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ 404 } 405 #endif 406 407 /********************************************************************* 408 * 409 * RTT lock configuration for embOS Simulation on Windows 410 * (Can also be used for generic RTT locking with embOS) 411 */ 412 #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) 413 414 void OS_SIM_EnterCriticalSection(void); 415 void OS_SIM_LeaveCriticalSection(void); 416 417 #define SEGGER_RTT_LOCK() { \ 418 OS_SIM_EnterCriticalSection(); 419 420 #define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ 421 } 422 #endif 423 424 /********************************************************************* 425 * 426 * RTT lock configuration fallback 427 */ 428 #ifndef SEGGER_RTT_LOCK 429 #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) 430 #endif 431 432 #ifndef SEGGER_RTT_UNLOCK 433 #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) 434 #endif 435 436 #endif 437 /*************************** End of file ****************************/ 438
