1 /*
2  * Trace Recorder for Tracealyzer v4.9.2
3  * Copyright 2023 Percepio AB
4  * www.percepio.com
5  *
6  * SPDX-License-Identifier: Apache-2.0
7  *
8  * The interface definitions for trace streaming ("stream ports").
9  * This "stream port" sets up the recorder to use UDP as streaming channel.
10  * The example is for lwIP.
11  */
12 
13 #ifndef TRC_STREAM_PORT_H
14 #define TRC_STREAM_PORT_H
15 
16 #include <stdint.h>
17 #include <trcTypes.h>
18 #include <trcStreamPortConfig.h>
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
24 #define TRC_ALIGNED_STREAM_PORT_BUFFER_SIZE ((((TRC_CFG_STREAM_PORT_INTERNAL_BUFFER_SIZE) + sizeof(TraceUnsignedBaseType_t) - 1) / sizeof(TraceUnsignedBaseType_t)) * sizeof(TraceUnsignedBaseType_t))
25 
26 #define TRC_USE_INTERNAL_BUFFER (TRC_CFG_STREAM_PORT_USE_INTERNAL_BUFFER)
27 
28 #define TRC_INTERNAL_EVENT_BUFFER_WRITE_MODE (TRC_CFG_STREAM_PORT_INTERNAL_BUFFER_WRITE_MODE)
29 
30 #define TRC_INTERNAL_EVENT_BUFFER_TRANSFER_MODE (TRC_CFG_STREAM_PORT_INTERNAL_BUFFER_TRANSFER_MODE)
31 
32 #define TRC_INTERNAL_BUFFER_CHUNK_SIZE (TRC_CFG_STREAM_PORT_INTERNAL_BUFFER_CHUNK_SIZE)
33 
34 #define TRC_INTERNAL_BUFFER_CHUNK_TRANSFER_AGAIN_SIZE_LIMIT (TRC_CFG_STREAM_PORT_INTERNAL_BUFFER_CHUNK_TRANSFER_AGAIN_SIZE_LIMIT)
35 
36 #define TRC_INTERNAL_BUFFER_CHUNK_TRANSFER_AGAIN_COUNT_LIMIT (TRC_CFG_STREAM_PORT_INTERNAL_BUFFER_CHUNK_TRANSFER_AGAIN_COUNT_LIMIT)
37 
38 typedef struct TraceStreamPortBuffer	/* Aligned */
39 {
40 #if (TRC_USE_INTERNAL_BUFFER)
41 	uint8_t buffer[(TRC_ALIGNED_STREAM_PORT_BUFFER_SIZE)];
42 #else
43 	TraceUnsignedBaseType_t buffer[1];
44 #endif
45 } TraceStreamPortBuffer_t;
46 
47 int32_t prvTraceUdpWrite(void* pvData, uint32_t uiSize, int32_t* piBytesWritten);
48 
49 int32_t prvTraceUdpRead(void* pvData, uint32_t uiSize, int32_t* piBytesRead);
50 
51 traceResult xTraceStreamPortInitialize(TraceStreamPortBuffer_t* pxBuffer);
52 
53 /**
54  * @brief Allocates data from the stream port.
55  *
56  * @param[in] uiSize Allocation size
57  * @param[out] ppvData Allocation data pointer
58  *
59  * @retval TRC_FAIL Allocate failed
60  * @retval TRC_SUCCESS Success
61  */
62 #if (TRC_USE_INTERNAL_BUFFER == 1)
63 	#if (TRC_INTERNAL_EVENT_BUFFER_WRITE_MODE == TRC_INTERNAL_EVENT_BUFFER_OPTION_WRITE_MODE_COPY)
64 		#define xTraceStreamPortAllocate(uiSize, ppvData) ((void)(uiSize), xTraceStaticBufferGet(ppvData))
65 	#else
66 		#define xTraceStreamPortAllocate(uiSize, ppvData) ((void)(uiSize), xTraceInternalEventBufferAlloc(uiSize, ppvData))
67 	#endif
68 #else
69 	#define xTraceStreamPortAllocate(uiSize, ppvData) ((void)(uiSize), xTraceStaticBufferGet(ppvData))
70 #endif
71 
72 /**
73  * @brief Commits data to the stream port, depending on the implementation/configuration of the
74  * stream port this data might be directly written to the stream port interface, buffered, or
75  * something else.
76  *
77  * @param[in] pvData Data to commit
78  * @param[in] uiSize Data to commit size
79  * @param[out] piBytesCommitted Bytes committed
80  *
81  * @retval TRC_FAIL Commit failed
82  * @retval TRC_SUCCESS Success
83  */
84 #if (TRC_USE_INTERNAL_BUFFER == 1)
85 	#if (TRC_INTERNAL_EVENT_BUFFER_WRITE_MODE == TRC_INTERNAL_EVENT_BUFFER_OPTION_WRITE_MODE_COPY)
86 		#define xTraceStreamPortCommit xTraceInternalEventBufferPush
87 	#else
88 		#define xTraceStreamPortCommit xTraceInternalEventBufferAllocCommit
89 	#endif
90 #else
91 	#define xTraceStreamPortCommit xTraceStreamPortWriteData
92 #endif
93 
94 #define xTraceStreamPortWriteData(pvData, uiSize, piBytesWritten) (prvTraceUdpWrite(pvData, uiSize, piBytesWritten) == 0 ? TRC_SUCCESS : TRC_FAIL)
95 
96 #define xTraceStreamPortReadData(pvData, uiSize, piBytesRead) (prvTraceUdpRead(pvData, uiSize, piBytesRead) == 0 ? TRC_SUCCESS : TRC_FAIL)
97 
98 #define xTraceStreamPortOnEnable(uiStartOption) ((void)(uiStartOption), TRC_SUCCESS)
99 
100 #define xTraceStreamPortOnDisable() (TRC_SUCCESS)
101 
102 #define xTraceStreamPortOnTraceBegin() (TRC_SUCCESS)
103 
104 traceResult xTraceStreamPortOnTraceEnd(void);
105 
106 #ifdef __cplusplus
107 }
108 #endif
109 
110 #endif /* TRC_STREAM_PORT_H */
111 
112