1 /* 2 * Copyright (c) 2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /** @file rpu_if.h 8 * @brief Common structures and definitions for RPU interface. 9 */ 10 11 #ifndef __RPU_IF_H__ 12 #define __RPU_IF_H__ 13 #include "pack_def.h" 14 15 /* Beginning address of the global RAM */ 16 #define RPU_ADDR_GRAM_START 0xB7000000 17 /* Ending address of the global RAM */ 18 #define RPU_ADDR_GRAM_END 0xB70101FF 19 /* Beginning address of the system bus register space */ 20 #define RPU_ADDR_SBUS_START 0xA4000000 21 /* Ending address of the system bus register space */ 22 #define RPU_ADDR_SBUS_END 0xA4007FFF 23 /* Beginning address of the peripheral bus register space */ 24 #define RPU_ADDR_PBUS_START 0xA5000000 25 /* Ending address of the peripheral bus register space */ 26 #define RPU_ADDR_PBUS_END 0xA503FFFF 27 /* Beginning address of the MIPS boot exception vector registers */ 28 #define RPU_ADDR_BEV_START 0xBFC00000 29 /* Ending address of the MIPS boot exception vector registers */ 30 #define RPU_ADDR_BEV_END 0xBFCFFFFF 31 /* Beginning address of the packet RAM */ 32 #define RPU_ADDR_PKTRAM_START 0xB0000000 33 /* Ending address of the packet RAM */ 34 #define RPU_ADDR_PKTRAM_END 0xB0030FFF 35 36 /* Starting address of the LMAC MCU (MCU) retention RAM */ 37 #define RPU_ADDR_LMAC_CORE_RET_START 0x80040000 38 /* Starting address of the UMAC MCU (MCU2) retention RAM */ 39 #define RPU_ADDR_UMAC_CORE_RET_START 0x80080000 40 41 /** 42 * @brief Regions in the MCU local memory. 43 * 44 * The MCU local memory in the nRF70 is divided into three regions: 45 * - ROM : Read-only memory region. 46 * - RETENTION : Retention memory region. 47 * - SCRATCH : Scratch memory region. 48 */ 49 enum RPU_MCU_ADDR_REGIONS { 50 RPU_MCU_ADDR_REGION_ROM = 0, 51 RPU_MCU_ADDR_REGION_RETENTION, 52 RPU_MCU_ADDR_REGION_SCRATCH, 53 RPU_MCU_ADDR_REGION_MAX, 54 }; 55 56 /** 57 * @brief Address limits of each MCU local memory region. 58 * 59 * A MCU local memory region is defined by its: 60 * - Start address, and 61 * - End address. 62 */ 63 struct rpu_addr_region { 64 unsigned int start; 65 unsigned int end; 66 }; 67 68 /** 69 * @brief Address map of the MCU memory. 70 * 71 * The MCU memory map consists of three regions: 72 * - ROM : Read-only memory region. 73 * - RETENTION : Retention memory region. 74 * - SCRATCH : Scratch memory region. 75 */ 76 struct rpu_addr_map { 77 struct rpu_addr_region regions[RPU_MCU_ADDR_REGION_MAX]; 78 }; 79 80 /** 81 * @brief Memory map of the MCUs in the RPU. 82 * 83 * The RPU consists of two MCUs: 84 * - MCU: For the LMAC. 85 * - MCU2 : For the UMAC. 86 * 87 * Each MCU memory consists of three regions: 88 * - ROM : Read-only memory region. 89 * - RETENTION : Retention memory region. 90 * - SCRATCH : Scratch memory region. 91 */ 92 static const struct rpu_addr_map RPU_ADDR_MAP_MCU[] = { 93 /* MCU - LMAC */ 94 { 95 { 96 {0x80000000, 0x80033FFF}, 97 {0x80040000, 0x8004BFFF}, 98 {0x80080000, 0x8008FFFF} 99 }, 100 }, 101 /* MCU2 - UMAC */ 102 { 103 { 104 {0x80000000, 0x800617FF}, 105 {0x80080000, 0x800A3FFF}, 106 {0x80100000, 0x80137FFF}, 107 } 108 }, 109 }; 110 111 /* Number of boot exception vectors for each MCU */ 112 #define RPU_MCU_MAX_BOOT_VECTORS 4 113 114 /** 115 * @brief Boot vector definition for a MCU in nRF70. 116 * 117 * The boot vectors for the MCUs in the nRF70 are defined by their: 118 * - Address, and 119 * - Value. 120 */ 121 struct rpu_mcu_boot_vector { 122 unsigned int addr; 123 unsigned int val; 124 }; 125 126 /** 127 * @brief Boot vectors for the MCUs in nRF70. 128 * 129 * The boot vectors for the MCUs in nRF70. 130 */ 131 struct rpu_mcu_boot_vectors { 132 struct rpu_mcu_boot_vector vectors[RPU_MCU_MAX_BOOT_VECTORS]; 133 }; 134 135 /* Base mask for the nRF70 memory map */ 136 #define RPU_ADDR_MASK_BASE 0xFF000000 137 /* Offset mask for the nRF70 memory map */ 138 #define RPU_ADDR_MASK_OFFSET 0x00FFFFFF 139 /* Offset mask for the boot exception vector */ 140 #define RPU_ADDR_MASK_BEV_OFFSET 0x000FFFFF 141 142 /* Address of the nRF70 interrupt register */ 143 #define RPU_REG_INT_FROM_RPU_CTRL 0xA4000400 144 /* Control bit for enabling/disabling of nRF70 interrupts */ 145 #define RPU_REG_BIT_INT_FROM_RPU_CTRL 17 146 147 /* Address of the nRF70 IRQ register */ 148 #define RPU_REG_INT_TO_MCU_CTRL 0xA4000480 149 150 /* Address of the nRF70 interrupt ack register */ 151 #define RPU_REG_INT_FROM_MCU_ACK 0xA4000488 152 /* Bit to set to ack nRF70 interrupt */ 153 #define RPU_REG_BIT_INT_FROM_MCU_ACK 31 154 155 /* Address of the nRF70 UMAC MCU interrupt enable register */ 156 #define RPU_REG_INT_FROM_MCU_CTRL 0xA4000494 157 /* Bit to set to enable UMAC MCU interrupts */ 158 #define RPU_REG_BIT_INT_FROM_MCU_CTRL 31 159 160 /* Address of the nRF70 register which points to LMAC patch memory address */ 161 #define RPU_REG_UCC_SLEEP_CTRL_DATA_0 0xA4002C2C 162 /* Address of the nRF70 register which points to UMAC patch memory address */ 163 #define RPU_REG_UCC_SLEEP_CTRL_DATA_1 0xA4002C30 164 /* Address of the register to soft reset the LMAC MCU */ 165 #define RPU_REG_MIPS_MCU_CONTROL 0xA4000000 166 /* Address of the register to soft reset the UMAC MCU */ 167 #define RPU_REG_MIPS_MCU2_CONTROL 0xA4000100 168 169 /* Address of the nRF70 interrupt status register */ 170 #define RPU_REG_MIPS_MCU_UCCP_INT_STATUS 0xA4000004 171 /* Bit to check for watchdog interrupt */ 172 #define RPU_REG_BIT_MIPS_WATCHDOG_INT_STATUS 1 173 174 /* Address of the nRF70 watchdog timer register */ 175 #define RPU_REG_MIPS_MCU_TIMER 0xA400004C /* 24 bit timer@core clock ticks*/ 176 /* Default watchdog timer value */ 177 #define RPU_REG_MIPS_MCU_TIMER_RESET_VAL 0xFFFFFF 178 179 /* Address of the nRF70 watchdog interrupt clear register */ 180 #define RPU_REG_MIPS_MCU_UCCP_INT_CLEAR 0xA400000C 181 /* Bit to clear the watchdog interrupt */ 182 #define RPU_REG_BIT_MIPS_WATCHDOG_INT_CLEAR 1 183 184 /* Registers to control indirect access to LMAC MCU local memory */ 185 /* The MCU local memory address needs to be programmed to the control register */ 186 #define RPU_REG_MIPS_MCU_SYS_CORE_MEM_CTRL 0xA4000030 187 /* The data to be written to the MCU local memory needs to be programmed to the data register */ 188 #define RPU_REG_MIPS_MCU_SYS_CORE_MEM_WDATA 0xA4000034 189 190 /* Boot exception vector registers for the LMAC MCU */ 191 #define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_0 0xA4000050 192 #define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_1 0xA4000054 193 #define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_2 0xA4000058 194 #define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_3 0xA400005C 195 196 /* Registers to control indirect access to LMAC MCU local memory */ 197 /* The MCU local memory address needs to be programmed to the control register */ 198 #define RPU_REG_MIPS_MCU2_SYS_CORE_MEM_CTRL 0xA4000130 199 /* The data to be written to the MCU local memory needs to be programmed to the data register */ 200 #define RPU_REG_MIPS_MCU2_SYS_CORE_MEM_WDATA 0xA4000134 201 /* Boot exception vector registers for the LMAC MCU */ 202 #define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_0 0xA4000150 203 #define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_1 0xA4000154 204 #define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_2 0xA4000158 205 #define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_3 0xA400015C 206 207 /* Bit which controls the power state of the nRF70 */ 208 #define RPU_REG_BIT_PS_CTRL 0 209 /* Bit which indicates hardware bus ready state of the nRF70 */ 210 #define RPU_REG_BIT_PS_STATE 1 211 /* Bit which indicates the firmware readiness of the nRF70 */ 212 #define RPU_REG_BIT_READY_STATE 2 213 /* Address which has information about the RX command base */ 214 #define RPU_MEM_RX_CMD_BASE 0xB7000D58 215 216 /* Address which has information about the host port queue manager (HPQM) */ 217 #define RPU_MEM_HPQ_INFO 0xB0000024 218 /* Address which has information about the TX command base */ 219 #define RPU_MEM_TX_CMD_BASE 0xB00000B8 220 221 /* Address which has OTP location containing the factory test program version */ 222 #define RPU_MEM_OTP_FT_PROG_VERSION 0xB0004FD8 223 /* Address which has the OTP flags */ 224 #define RPU_MEM_OTP_INFO_FLAGS 0xB0004FDC 225 /* Address which has the OTP package type */ 226 #define RPU_MEM_OTP_PACKAGE_TYPE 0xB0004FD4 227 228 /* Base address of the area where TX/RX packet buffers can be programmed for transmission/reception */ 229 #define RPU_MEM_PKT_BASE 0xB0005000 230 /* Magic value to indicate start of the command counter synchronization between host and nRF70 */ 231 #define RPU_CMD_START_MAGIC 0xDEAD 232 /* Maximum size of the RX data command */ 233 #define RPU_DATA_CMD_SIZE_MAX_RX 8 234 /* Maximum size of the TX data command */ 235 #define RPU_DATA_CMD_SIZE_MAX_TX 148 236 /* Maximum size of the most common events */ 237 #define RPU_EVENT_COMMON_SIZE_MAX 128 238 239 /* Maximum event size */ 240 #define MAX_EVENT_POOL_LEN 1000 241 /* Maximum number of RX queues */ 242 #define MAX_NUM_OF_RX_QUEUES 3 243 244 /* Packet RAM size in the nRF70 */ 245 #define RPU_PKTRAM_SIZE (RPU_ADDR_PKTRAM_END - RPU_MEM_PKT_BASE + 1) 246 247 /* Base address of the area where ADC output IQ samples are stored */ 248 #define RPU_MEM_RF_TEST_CAP_BASE 0xB0006000 249 250 /* OTP address offsets (word offsets) */ 251 #define REGION_PROTECT 64 252 #define PRODTEST_FT_PROGVERSION 29 253 #define PRODTEST_TRIM0 32 254 #define PRODTEST_TRIM1 33 255 #define PRODTEST_TRIM2 34 256 #define PRODTEST_TRIM3 35 257 #define PRODTEST_TRIM4 36 258 #define PRODTEST_TRIM5 37 259 #define PRODTEST_TRIM6 38 260 #define PRODTEST_TRIM7 39 261 #define PRODTEST_TRIM8 40 262 #define PRODTEST_TRIM9 41 263 #define PRODTEST_TRIM10 42 264 #define PRODTEST_TRIM11 43 265 #define PRODTEST_TRIM12 44 266 #define PRODTEST_TRIM13 45 267 #define PRODTEST_TRIM14 46 268 #define INFO_PART 48 269 #define INFO_VARIANT 49 270 #define INFO_UUID 52 271 #define QSPI_KEY 68 272 #define MAC0_ADDR 72 273 #define MAC1_ADDR 74 274 #define CALIB_XO 76 275 #define REGION_DEFAULTS 85 276 #define PRODRETEST_PROGVERSION 86 277 #define PRODRETEST_TRIM0 87 278 #define PRODRETEST_TRIM1 88 279 #define PRODRETEST_TRIM2 89 280 #define PRODRETEST_TRIM3 90 281 #define PRODRETEST_TRIM4 91 282 #define PRODRETEST_TRIM5 92 283 #define PRODRETEST_TRIM6 93 284 #define PRODRETEST_TRIM7 94 285 #define PRODRETEST_TRIM8 95 286 #define PRODRETEST_TRIM9 96 287 #define PRODRETEST_TRIM10 97 288 #define PRODRETEST_TRIM11 98 289 #define PRODRETEST_TRIM12 99 290 #define PRODRETEST_TRIM13 100 291 #define PRODRETEST_TRIM14 101 292 #define OTP_MAX_WORD_LEN 128 293 #define QSPI_KEY_LENGTH_BYTES 16 294 #define RETRIM_LEN 15 295 296 /* Size of XO calibration value stored in the OTP field CALIB_XO */ 297 #define OTP_SZ_CALIB_XO 1 298 299 /* Byte offsets of XO calib value in CALIB_XO field in the OTP */ 300 #define OTP_OFF_CALIB_XO 0 301 302 /* Masks to program bit fields in REGION_DEFAULTS field in the OTP */ 303 #define QSPI_KEY_FLAG_MASK ~(1U<<0) 304 #define MAC0_ADDR_FLAG_MASK ~(1U<<1) 305 #define MAC1_ADDR_FLAG_MASK ~(1U<<2) 306 #define CALIB_XO_FLAG_MASK ~(1U<<3) 307 308 /* RF register address to facilitate OTP access */ 309 #define OTP_VOLTCTRL_ADDR 0x19004 310 /* Voltage value to be written into the above RF register for OTP write access */ 311 #define OTP_VOLTCTRL_2V5 0x3b 312 /* Voltage value to be written into the above RF register for OTP read access */ 313 #define OTP_VOLTCTRL_1V8 0xb 314 315 #define OTP_POLL_ADDR 0x01B804 316 #define OTP_WR_DONE 0x1 317 #define OTP_READ_VALID 0x2 318 #define OTP_READY 0x4 319 320 321 #define OTP_RWSBMODE_ADDR 0x01B800 322 #define OTP_READ_MODE 0x1 323 #define OTP_BYTE_WRITE_MODE 0x42 324 325 326 #define OTP_RDENABLE_ADDR 0x01B810 327 #define OTP_READREG_ADDR 0x01B814 328 329 #define OTP_WRENABLE_ADDR 0x01B808 330 #define OTP_WRITEREG_ADDR 0x01B80C 331 332 #define OTP_TIMING_REG1_ADDR 0x01B820 333 #define OTP_TIMING_REG1_VAL 0x0 334 #define OTP_TIMING_REG2_ADDR 0x01B824 335 #define OTP_TIMING_REG2_VAL 0x030D8B 336 337 #define OTP_FRESH_FROM_FAB 0xFFFFFFFF 338 #define OTP_PROGRAMMED 0x00000000 339 #define OTP_ENABLE_PATTERN 0x50FA50FA 340 #define OTP_INVALID 0xDEADBEEF 341 342 #define FT_PROG_VER_MASK 0xF0000 343 344 /** 345 * @brief RX buffer related information to be passed to nRF70. 346 * 347 * This structure encapsulates the information to be passed to nRF70 for 348 * buffers which the nRf70 will use to pass the received frames. 349 */ 350 struct host_rpu_rx_buf_info { 351 /** Address in the host memory where the RX buffer is located. */ 352 unsigned int addr; 353 } __NRF_WIFI_PKD; 354 355 /** 356 * @brief Hostport Queue (HPQ) information. 357 * 358 * This structure encapsulates the information which represents a HPQ. 359 */ 360 struct host_rpu_hpq { 361 /** HPQ address where the host can post the address of a message intended for the RPU. */ 362 unsigned int enqueue_addr; 363 /** HPQ address where the host can get the address of a message intended for the host. */ 364 unsigned int dequeue_addr; 365 } __NRF_WIFI_PKD; 366 367 /** 368 * @brief Information about Hostport Queues (HPQ) to be used 369 * for exchanging information between the Host and RPU. 370 * 371 * Hostport queue information passed by the RPU to the host, which the host can 372 * use, to communicate with the RPU. 373 */ 374 struct host_rpu_hpqm_info { 375 /** Queue which the RPU uses to inform the host about events. */ 376 struct host_rpu_hpq event_busy_queue; 377 /** Queue on which the consumed events are pushed so that RPU can reuse them. */ 378 struct host_rpu_hpq event_avl_queue; 379 /** Queue used by the host to push commands to the RPU. */ 380 struct host_rpu_hpq cmd_busy_queue; 381 /** Queue which RPU uses to inform host about command buffers which can be used to 382 * push commands to the RPU. 383 */ 384 struct host_rpu_hpq cmd_avl_queue; 385 /** Queue used by the host to push RX buffers to the RPU. */ 386 struct host_rpu_hpq rx_buf_busy_queue[MAX_NUM_OF_RX_QUEUES]; 387 } __NRF_WIFI_PKD; 388 389 /** 390 * @brief Common header included in each command/event. 391 * This structure encapsulates the common information included at the start of 392 * each command/event exchanged with the RPU. 393 */ 394 struct host_rpu_msg_hdr { 395 /** Length of the message. */ 396 unsigned int len; 397 /** Flag to indicate whether the recipient is expected to resubmit the 398 * cmd/event address back to the trasmitting entity. 399 */ 400 unsigned int resubmit; 401 } __NRF_WIFI_PKD; 402 403 #endif /* __RPU_IF_H__ */ 404
