1# Current implementation status 2 3Currently peripherals of a nRF52833 and nrf5340 SOCs are modelled at varying degrees: 4 5Notation: 6 7| Mark | Meaning | 8|---|---| 9| ✅ | Fully completed | 10| ✔ | Implemented | 11| ☐ | Minimal/stubbed implementation | 12| 𐄂 | Missing | 13 14<br> 15 16| | | **nRF52833** | **nRF5340** | **nRF54L15** | Notes | 17|-----------------|------------------------------------------------------------|--------------|-------------|--------------|----------------------------------------------------------------------------------------------------------------------------| 18| **AAR** | Accelerated address resolver | ✔ | ✔ | 𐄂 | See [NHW_AAR.c](../src/HW_models/NHW_AAR.c) | 19| **ACL** | Access control lists | 𐄂 | 𐄂 | N/A | | 20| **CACHE** | Instruction/data cache | N/A | 𐄂 | 𐄂 | | 21| **CCM** | AES CCM mode encryption | ✔ | ✔ | 𐄂 | See [NHW_AES_CCM.c](../src/HW_models/NHW_AES_CCM.c) | 22| **CLOCK** | Clock control | ✔ | ✔ | ☐ | For 52 & 53 see [NHW_CLOCK.c](../src/HW_models/NHW_CLOCK.c). For 54L see [NHW_54L_CLOCK.c](../src/HW_models/NHW_54L_CLOCK.c) | 23| **COMP** | Comparator | 𐄂 | 𐄂 | 𐄂 | | 24| **CRACEN** | | N/A | N/A | 𐄂 | | 25| **DPPI** | Distributed programmable peripheral interconnect | N/A | ✅ | ✅ | | 26| **ECB** | AES electronic codebook mode encryption | ✅ | ✅ | 𐄂 | | 27| **EGU** | Event generator unit | ✅ | ✅ | ✅ | | 28| **FICR** | Factory information configuration registers | ✔ | ✔ | ✔ | For 52: See [NHW_52_FICR.c](../src/HW_models/NHW_52_FICR.c)<br>For 53: See [NHW_53_FICR.c](../src/HW_models/NHW_53_FICR.c) | 29| **GLITCHDET** | Voltage glitch detectors | N/A | N/A | 𐄂 | | 30| **GPIO** | General purpose input/output | ✔ | 𐄂 | 𐄂 | For 52: See [NRF_GPIO.c](../src/HW_models/NRF_GPIO.c) | 31| **GPIOTE** | GPIO tasks and events | ✅ | 𐄂 | 𐄂 | For 52: Complete with very minor differences, see [NRF_GPIOTE.c](../src/HW_models/NRF_GPIOTE.c) | 32| **GRTC** | Global real-time counter | N/A | N/A | ✔ | | 33| **I2S** | Inter-IC sound interface | 𐄂 | 𐄂 | 𐄂 | | 34| **IPC** | Interprocessor communication | N/A | ✔ | N/A | See [NHW_IPC.c](../src/HW_models/NHW_IPC.c) | 35| **KMU** | Key management unit | N/A | 𐄂 | 𐄂 | | 36| **LPCOMP** | Low-power comparator | 𐄂 | 𐄂 | 𐄂 | | 37| **MEMCONF** | Memory configuration | N/A | N/A | 𐄂 | | 38| **MPC** | Memory Privilege Controller | N/A | N/A | 𐄂 | | 39| **MUTEX** | Mutual exclusive peripheral | N/A | ✅ | N/A | | 40| **MWU** | Memory watch unit | 𐄂 | N/A | N/A | | 41| **NFCT** | Near field communication tag | 𐄂 | 𐄂 | 𐄂 | | 42| **NVMC** | Non-volatile memory controller | ✔ | ✔ | N/A | See [NHW_NVMC.c](../src/HW_models/NHW_NVMC.c) | 43| **OSCILLATORS** | Oscillator control | N/A | 𐄂 | 𐄂 | | 44| **PDM** | Pulse density modulation interface | 𐄂 | 𐄂 | 𐄂 | | 45| **POWER** | Power supply | ☐ | ☐ | ☐ | Only register stubs | 46| **PPI** | Programmable peripheral interconnect | ✅ | N/A | N/A | Complete but some peripheral connections are missing | 47| **PPIB** | PPI Bridge | N/A | N/A | ✔ | | 48| **PWM** | Pulse width modulation | 𐄂 | 𐄂 | 𐄂 | | 49| **QDEC** | Quadrature decoder | 𐄂 | 𐄂 | 𐄂 | | 50| **RADIO** | 2.4 GHz radio | ✔ | ✔ | ✔ | See [NHW_RADIO.c](../src/HW_models/NHW_RADIO.c) | 51| **REGULATORS** | Regulator control | N/A | 𐄂 | 𐄂 | | 52| **RESET** | Reset control | N/A | ☐ | ☐ | Only register stubs | 53| **RNG** | Random number generator | ✔ | ✔ | N/A | See [NHW_RNG.c](../src/HW_models/NHW_RNG.c) | 54| **RRAMC** | Resistive random access memory controller | N/A | N/A | ✔ | See [NHW_RRAMC.c](../src/HW_models/NHW_RRAMC.c) | 55| **RTC** | Real-time counter | ✔ | ✔ | ✔ | See [NHW_RTC.c](../src/HW_models/NHW_RTC.c) | 56| **SAADC** | Successive approximation analog-to-digital converter | 𐄂 | 𐄂 | 𐄂 | | 57| **[Q]SPI[M/S]** | [Quad] Serial peripheral interface [master/slave] | 𐄂 | 𐄂 | 𐄂 | | 58| **SPU** | System protection unit | N/A | 𐄂 | 𐄂 | | 59| **SWI** | Software interrupts | ✅ | ✅ | ✅ | | 60| **TAMPC** | Tamper controller | N/A | N/A | 𐄂 | | 61| **TEMP** | Temperature sensor | ✔ | ✔ | ✔ | See [NHW_TEMP.c](../src/HW_models/NHW_TEMP.c) | 62| **TIMER** | Timer/counter | ✅ | ✅ | ✅ | | 63| **TWI[M/S]** | I2C compatible two-wire interface | 𐄂 | 𐄂 | 𐄂 | | 64| **UART[E]** | Universal asynchronous receiver/transmitter [with EasyDMA] | ✔ | ✔ | 𐄂 | For 53: It cannot be used yet w Zephyr as the Zephyr driver requires a working nRF53 GPIO | 65| **UICR** | User information configuration registers | ✔ | ✔ | ✔ | See [NHW_NVMC.c](../src/HW_models/NHW_NVMC.c) | 66| **USBD** | Universal serial bus device | 𐄂 | 𐄂 | N/A | | 67| **USBREG** | Universal serial bus device | N/A | 𐄂 | N/A | | 68| **VMC** | Volatile memory controller | N/A | 𐄂 | N/A | | 69| **VREQCTRL** | Voltage request control | N/A | ☐ | N/A | Only register stubs | 70| **WDT** | Watchdog timer | 𐄂 | 𐄂 | 𐄂 | | 71 72ARM processor peripherals or the AHB interconnect are not part of these models 73
