1/***************************************************************************//**
2* \file cy8c6xxa_cm0plus.ld
3* \version 2.60
4*
5* Linker file for the GNU C compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point location is fixed and starts at 0x10000000. The valid
12* application image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2019 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
39SEARCH_DIR(.)
40GROUP(-lgcc -lc -lnosys)
41ENTRY(Reset_Handler)
42
43/* Size of the stack section at the end of CM0+ SRAM */
44STACK_SIZE = 0x1000;
45
46/* Force symbol to be entered in the output file as an undefined symbol. Doing
47* this may, for example, trigger linking of additional modules from standard
48* libraries. You may list several symbols for each EXTERN, and you may use
49* EXTERN multiple times. This command has the same effect as the -u command-line
50* option.
51*/
52EXTERN(Reset_Handler)
53
54/* The MEMORY section below describes the location and size of blocks of memory in the target.
55* Use this section to specify the memory regions available for allocation.
56*/
57MEMORY
58{
59    /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
60     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
61     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
62     * Using this memory region for other purposes will lead to unexpected behavior.
63     * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
64     * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
65     */
66    public_ram        (rw)    : ORIGIN = 0x08000000, LENGTH = 0x800
67    ram               (rwx)   : ORIGIN = 0x08000800, LENGTH = 0x1F800
68    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x18000
69
70    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
71     * You can assign sections to this memory region for only one of the cores.
72     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
73     * Therefore, repurposing this memory region will prevent such middleware from operation.
74     */
75    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
76
77    /* The following regions define device specific memory regions and must not be changed. */
78    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
79    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
80    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
81    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
82    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
83    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
84    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
85}
86
87/* Library configurations */
88GROUP(libgcc.a libc.a libm.a libnosys.a)
89
90/* Linker script to place sections and symbol values. Should be used together
91 * with other linker script that defines memory regions FLASH and RAM.
92 * It references following symbols, which must be defined in code:
93 *   Reset_Handler : Entry of reset handler
94 *
95 * It defines following symbols, which code can use without definition:
96 *   __exidx_start
97 *   __exidx_end
98 *   __copy_table_start__
99 *   __copy_table_end__
100 *   __zero_table_start__
101 *   __zero_table_end__
102 *   __etext
103 *   __data_start__
104 *   __preinit_array_start
105 *   __preinit_array_end
106 *   __init_array_start
107 *   __init_array_end
108 *   __fini_array_start
109 *   __fini_array_end
110 *   __data_end__
111 *   __bss_start__
112 *   __bss_end__
113 *   __end__
114 *   end
115 *   __HeapLimit
116 *   __StackLimit
117 *   __StackTop
118 *   __stack
119 *   __Vectors_End
120 *   __Vectors_Size
121 */
122
123
124SECTIONS
125{
126    .cy_app_header :
127    {
128        KEEP(*(.cy_app_header))
129    } > flash
130
131    /* Cortex-M0+ application flash area */
132    .text :
133    {
134        . = ALIGN(4);
135        __Vectors = . ;
136        KEEP(*(.vectors))
137        . = ALIGN(4);
138        __Vectors_End = .;
139        __Vectors_Size = __Vectors_End - __Vectors;
140        __end__ = .;
141
142        . = ALIGN(4);
143        *(.text*)
144
145        KEEP(*(.init))
146        KEEP(*(.fini))
147
148        /* .ctors */
149        *crtbegin.o(.ctors)
150        *crtbegin?.o(.ctors)
151        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
152        *(SORT(.ctors.*))
153        *(.ctors)
154
155        /* .dtors */
156        *crtbegin.o(.dtors)
157        *crtbegin?.o(.dtors)
158        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
159        *(SORT(.dtors.*))
160        *(.dtors)
161
162        /* Read-only code (constants). */
163        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
164
165        KEEP(*(.eh_frame*))
166    } > flash
167
168
169    .ARM.extab :
170    {
171        *(.ARM.extab* .gnu.linkonce.armextab.*)
172    } > flash
173
174    __exidx_start = .;
175
176    .ARM.exidx :
177    {
178        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
179    } > flash
180    __exidx_end = .;
181
182
183    /* To copy multiple ROM to RAM sections,
184     * uncomment .copy.table section and,
185     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
186    .copy.table :
187    {
188        . = ALIGN(4);
189        __copy_table_start__ = .;
190
191        /* Copy interrupt vectors from flash to RAM */
192        LONG (__Vectors)                                    /* From */
193        LONG (__ram_vectors_start__)                        /* To   */
194        LONG (__Vectors_End - __Vectors)                    /* Size */
195
196        /* Copy data section to RAM */
197        LONG (__etext)                                      /* From */
198        LONG (__data_start__)                               /* To   */
199        LONG (__data_end__ - __data_start__)                /* Size */
200
201        __copy_table_end__ = .;
202    } > flash
203
204
205    /* To clear multiple BSS sections,
206     * uncomment .zero.table section and,
207     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */
208    .zero.table :
209    {
210        . = ALIGN(4);
211        __zero_table_start__ = .;
212        LONG (__bss_start__)
213        LONG (__bss_end__ - __bss_start__)
214        __zero_table_end__ = .;
215    } > flash
216
217    __etext =  . ;
218
219    /* Set stack top to end of RAM, and stack limit move down by
220     * size of stack_dummy section */
221    __StackTop = ORIGIN(ram) + LENGTH(ram);
222    __StackLimit = __StackTop - STACK_SIZE ;
223    PROVIDE(__stack = __StackTop);
224
225    .stackSpace (NOLOAD) : ALIGN(8)
226    {
227        . = . + STACK_SIZE ;
228    } > ram
229
230    .ramVectors (NOLOAD) : ALIGN(8)
231    {
232        __ram_vectors_start__ = .;
233        KEEP(*(.ram_vectors))
234        __ram_vectors_end__   = .;
235    } > ram
236
237    /* Unprotected public RAM */
238    .cy_sharedmem (NOLOAD):
239    {
240        . = ALIGN(4);
241        __public_ram_start__ = .;
242        KEEP(*(.cy_sharedmem))
243        . = ALIGN(4);
244        __public_ram_end__ = .;
245    } > public_ram
246
247    .data __ram_vectors_end__ : AT (__etext)
248    {
249        __data_start__ = .;
250
251        *(vtable)
252        *(.data*)
253
254        . = ALIGN(4);
255        /* preinit data */
256        PROVIDE_HIDDEN (__preinit_array_start = .);
257        KEEP(*(.preinit_array))
258        PROVIDE_HIDDEN (__preinit_array_end = .);
259
260        . = ALIGN(4);
261        /* init data */
262        PROVIDE_HIDDEN (__init_array_start = .);
263        KEEP(*(SORT(.init_array.*)))
264        KEEP(*(.init_array))
265        PROVIDE_HIDDEN (__init_array_end = .);
266
267        . = ALIGN(4);
268        /* finit data */
269        PROVIDE_HIDDEN (__fini_array_start = .);
270        KEEP(*(SORT(.fini_array.*)))
271        KEEP(*(.fini_array))
272        PROVIDE_HIDDEN (__fini_array_end = .);
273
274        KEEP(*(.jcr*))
275        . = ALIGN(4);
276
277        KEEP(*(.cy_ramfunc*))
278        . = ALIGN(4);
279
280        __data_end__ = .;
281
282    } > ram
283
284
285    /* Place variables in the section that should not be initialized during the
286    *  device startup.
287    */
288    .noinit (NOLOAD) : ALIGN(8)
289    {
290      KEEP(*(.noinit))
291    } > ram
292
293
294    /* The uninitialized global or static variables are placed in this section.
295    *
296    * The NOLOAD attribute tells linker that .bss section does not consume
297    * any space in the image. The NOLOAD attribute changes the .bss type to
298    * NOBITS, and that  makes linker to A) not allocate section in memory, and
299    * A) put information to clear the section with all zeros during application
300    * loading.
301    *
302    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
303    * This  makes linker to A) allocate zeroed section in memory, and B) copy
304    * this section to RAM during application loading.
305    */
306    .bss (NOLOAD):
307    {
308        . = ALIGN(4);
309        __bss_start__ = .;
310        *(.bss*)
311        *(COMMON)
312        . = ALIGN(4);
313        __bss_end__ = .;
314    } > ram
315
316    .heap (NOLOAD):
317    {
318        __HeapBase = .;
319        __end__ = .;
320        end = __end__;
321        KEEP(*(.heap*))
322        . = ORIGIN(ram) + LENGTH(ram);
323        __HeapLimit = .;
324    } > ram
325
326
327    /* Emulated EEPROM Flash area */
328    .cy_em_eeprom :
329    {
330        KEEP(*(.cy_em_eeprom))
331    } > em_eeprom
332
333
334    /* Supervisory Flash: User data */
335    .cy_sflash_user_data :
336    {
337        KEEP(*(.cy_sflash_user_data))
338    } > sflash_user_data
339
340
341    /* Supervisory Flash: Normal Access Restrictions (NAR) */
342    .cy_sflash_nar :
343    {
344        KEEP(*(.cy_sflash_nar))
345    } > sflash_nar
346
347
348    /* Supervisory Flash: Public Key */
349    .cy_sflash_public_key :
350    {
351        KEEP(*(.cy_sflash_public_key))
352    } > sflash_public_key
353
354
355    /* Supervisory Flash: Table of Content # 2 */
356    .cy_toc_part2 :
357    {
358        KEEP(*(.cy_toc_part2))
359    } > sflash_toc_2
360
361
362    /* Supervisory Flash: Table of Content # 2 Copy */
363    .cy_rtoc_part2 :
364    {
365        KEEP(*(.cy_rtoc_part2))
366    } > sflash_rtoc_2
367
368
369    /* Places the code in the Execute in Place (XIP) section. See the smif driver
370    *  documentation for details.
371    */
372    .cy_xip :
373    {
374        KEEP(*(.cy_xip))
375    } > xip
376
377
378    /* eFuse */
379    .cy_efuse :
380    {
381        KEEP(*(.cy_efuse))
382    } > efuse
383
384
385    /* These sections are used for additional metadata (silicon revision,
386    *  Silicon/JTAG ID, etc.) storage.
387    */
388    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
389}
390
391
392/* The following symbols used by the cymcuelftool. */
393/* Flash */
394__cy_memory_0_start    = 0x10000000;
395__cy_memory_0_length   = 0x00200000;
396__cy_memory_0_row_size = 0x200;
397
398/* Emulated EEPROM Flash area */
399__cy_memory_1_start    = 0x14000000;
400__cy_memory_1_length   = 0x8000;
401__cy_memory_1_row_size = 0x200;
402
403/* Supervisory Flash */
404__cy_memory_2_start    = 0x16000000;
405__cy_memory_2_length   = 0x8000;
406__cy_memory_2_row_size = 0x200;
407
408/* XIP */
409__cy_memory_3_start    = 0x18000000;
410__cy_memory_3_length   = 0x08000000;
411__cy_memory_3_row_size = 0x200;
412
413/* eFuse */
414__cy_memory_4_start    = 0x90700000;
415__cy_memory_4_length   = 0x100000;
416__cy_memory_4_row_size = 1;
417
418/* EOF */
419