1 /*******************************************************************************
2 * File Name: cycfg_pins.c
3 *
4 * Description:
5 * Pin configuration
6 * This file was automatically generated and should not be modified.
7 * Device Configurator: 2.0.0.1483
8 * Device Support Library (../../../psoc6pdl): 1.3.1.1499
9 *
10 ********************************************************************************
11 * Copyright 2017-2019 Cypress Semiconductor Corporation
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 ********************************************************************************/
26
27 #include "cycfg_pins.h"
28
29 const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config =
30 {
31 .outVal = 1,
32 .driveMode = CY_GPIO_DM_HIGHZ,
33 .hsiom = CYBSP_UART_RX_HSIOM,
34 .intEdge = CY_GPIO_INTR_DISABLE,
35 .intMask = 0UL,
36 .vtrip = CY_GPIO_VTRIP_CMOS,
37 .slewRate = CY_GPIO_SLEW_FAST,
38 .driveSel = CY_GPIO_DRIVE_1_2,
39 .vregEn = 0UL,
40 .ibufMode = 0UL,
41 .vtripSel = 0UL,
42 .vrefSel = 0UL,
43 .vohSel = 0UL,
44 };
45 #if defined (CY_USING_HAL)
46 const cyhal_resource_inst_t CYBSP_UART_RX_obj =
47 {
48 .type = CYHAL_RSC_GPIO,
49 .block_num = CYBSP_UART_RX_PORT_NUM,
50 .channel_num = CYBSP_UART_RX_PIN,
51 };
52 #endif //defined (CY_USING_HAL)
53 const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config =
54 {
55 .outVal = 1,
56 .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
57 .hsiom = CYBSP_UART_TX_HSIOM,
58 .intEdge = CY_GPIO_INTR_DISABLE,
59 .intMask = 0UL,
60 .vtrip = CY_GPIO_VTRIP_CMOS,
61 .slewRate = CY_GPIO_SLEW_FAST,
62 .driveSel = CY_GPIO_DRIVE_1_2,
63 .vregEn = 0UL,
64 .ibufMode = 0UL,
65 .vtripSel = 0UL,
66 .vrefSel = 0UL,
67 .vohSel = 0UL,
68 };
69 #if defined (CY_USING_HAL)
70 const cyhal_resource_inst_t CYBSP_UART_TX_obj =
71 {
72 .type = CYHAL_RSC_GPIO,
73 .block_num = CYBSP_UART_TX_PORT_NUM,
74 .channel_num = CYBSP_UART_TX_PIN,
75 };
76 #endif //defined (CY_USING_HAL)
77
init_cycfg_pins(void)78 void init_cycfg_pins(void)
79 {
80 Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config);
81 #if defined (CY_USING_HAL)
82 cyhal_hwmgr_reserve(&CYBSP_UART_RX_obj);
83 #endif //defined (CY_USING_HAL)
84
85 Cy_GPIO_Pin_Init(CYBSP_UART_TX_PORT, CYBSP_UART_TX_PIN, &CYBSP_UART_TX_config);
86 #if defined (CY_USING_HAL)
87 cyhal_hwmgr_reserve(&CYBSP_UART_TX_obj);
88 #endif //defined (CY_USING_HAL)
89 }
90
